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參數(shù)資料
| 型號： | M48Z129V-70PM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| 中文描述： | 3.3V/5V的1兆位的SRAM 128KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 94K |
| 代理商： | M48Z129V-70PM1 |
3/13
M48Z129Y, M48Z129V
WRITE MODE
The M48Z129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are active.
The start of a write is referenced from the latter oc-
curring falling edge of W or E. A write is terminat-
ed by the earlier rising edge of W or E. The
addresses must be held valid throughout the cycle.
E or W must return high for a minimum of t
EHAX
from Chip Enable or t
WHAX
from Write Enable prior
to the initiation of another read or write cycle.
Data-in must be valid t
DVWH
prior to the end of
write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W
will disable the outputs t
WLQZ
after W falls.
DATA RETENTION MODE
With valid V
CC
applied, the M48Z129Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when V
CC
falls between V
PFD
(max), V
PFD
(min) window. All
outputs become high impedance and all inputs are
treated as “don’t care”.
Table 3. Operating Modes
(1)
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.5V to 5.5V
(M48Z129Y)
or
3.0V to 3.6V
(M48Z129V)
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO
(2)
X
X
X
High Z
Battery Back-up Mode
Figure 3. Block Diagram
AI03608
RST
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
A0-A16
DQ0-DQ7
E
W
G
POWER
VCC
BL
E
INTERNAL
BATTERY
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| M48Z129V-85PM1 | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129VPM | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z19-100PC1 | CMOS 8K x 8 ZEROPOWER SRAM |
| M48Z2M1-70PL1 | 16 Mb 2Mb x 8 ZEROPOWER SRAM |
| M48Z2M1Y-70PL1 | 16 Mb 2Mb x 8 ZEROPOWER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z129V-70PMTR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM |
| M48Z129V-85PM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM |
| M48Z129V-85PM1 | 功能描述:NVRAM 1M (128Kx8) 85ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| M48Z129V-85PM1 | 制造商:STMicroelectronics 功能描述:NVRAM 10 YR BATTERY 1MB 48Z129 |
| M48Z129V-85PMTR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM |
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