參數(shù)資料
型號(hào): M48Z129V-70PM1
廠商: 意法半導(dǎo)體
英文描述: 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM
中文描述: 3.3V/5V的1兆位的SRAM 128KB的x8 ZEROPOWER
文件頁(yè)數(shù): 4/13頁(yè)
文件大?。?/td> 94K
代理商: M48Z129V-70PM1
M48Z129Y, M48Z129V
4/13
Note
: A power failure during a write cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V
PFD
(min), the memory will be
in a write protected state, provided the V
CC
fall
time is not less than t
F
. The M48Z129Y/V may re-
spond to transient noise spikes on V
CC
that cross
into the deselect window during the time the de-
vice is sampling V
CC
. Therefore, decoupling of the
power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit
switches power to the internal battery, preserving
data. The internal energy source will maintain
data in the M48Z129Y/V for an accumulated peri-
od of at least 10 years at room temperature. As
system power rises above V
SO
, the battery is dis-
connected, and the power supply is switched to
external V
CC
. Deselect continues for t
REC
after
V
CC
reaches V
PFD
(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET OUTPUT
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M48Z129Y/V has a reset output (RST) pin which
is guaranteed to be low below V
PFD
(min). This sig-
nal is an open drain configuration. An appropriate
pull-up resistor should be chosen to control the
rise time. This signal will be valid for all voltage
conditions, even when V
CC
equals V
SS
. Once V
CC
exceeds the power failure detect voltage V
PFD
, an
internal timer keeps RST low for t
REC
to allow the
power supply to stabilize.
BATTERY LOW PIN
The M48Z129Y/V automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of 24 hours. The Bat-
tery Low (BL) pin will be asserted if the battery volt-
age is found to be less than approximately 2.5V. If
a battery low is generated during a power-up se-
quence, this indicates that the battery is below 2.5
volts and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
CC
is
supplied.
The M48Z129Y/V only monitors the battery when
a nominal V
CC
is applied to the device. Thus ap-
plications which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if
a battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor should be chosen
to control the rise time.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. AC Testing Load Circuit
Note: 1. 50pF for M48Z129V (3.3V).
AI03630
CL = 100pF
or 50pF
(1)
CL includes JIG capacitance
650
DEVICE
UNDER
TEST
1.75V
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參數(shù)描述
M48Z129V-70PMTR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM
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M48Z129V-85PM1 功能描述:NVRAM 1M (128Kx8) 85ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類(lèi)型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube
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M48Z129V-85PMTR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM