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參數(shù)資料
| 型號： | M52S128168A-7.5BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, FBGA-54 |
| 文件頁數(shù)： | 14/47頁 |
| 文件大小： | 1213K |
| 代理商： | M52S128168A-7.5BG |
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ES MT
DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
Preliminary
M52S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
14/47
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
RAS (min)
and “t
RP
” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
BOTH BANKS PRECHARGE
A11 banks can be precharged at the same time by using
Precharge all command. Asserting low on CS ,RAS , and
WE
with high on A10/AP after all banks have satisfied t
RAS
(min)
requirement, performs precharge on all banks. At the
end of t
RP
after performing precharge all, all banks are in idle
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and
WE
. The auto refresh command can only be asserted
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by t
RFC (min)
. The minimum number of clock cycles
required can be calculated by driving t
RFC
with clock cycle
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
from all banks idle state by asserting low on CS ,
RAS , CAS and CKE with high on
WE
. Once the self
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of t
RFC
before the SDRAM
reaches idle state to begin normal operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52S128168A-7.5TG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S16161A | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52S16161A-10BG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52S16161A-10TG | 512K x 16Bit x 2Banks Synchronous DRAM |
| M52S16161A-8BG | 512K x 16Bit x 2Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52S128168A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128324A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M52S128324A-10BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M52S128324A-10TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
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