參數(shù)資料
型號: M52S128168A-7.5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, FBGA-54
文件頁數(shù): 32/47頁
文件大小: 1213K
代理商: M52S128168A-7.5BG
ES MT
Power Up Sequence
Preliminary
M52S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
May. 2007
32/47
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
-
Apply VDD before or at the same time as VDDQ
-
Apply VDDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK,CLK),apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS..
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