M5M29KE131BTP
Renesas LSIs
Rev.1.1_48a_bezz
12
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
7) RA=Read Address: A22-A7 (block address, page address) must be valid.
8) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)
9) In case of Bottom 64M-bit area, A22 must be set to VIL.
In case of Top 64M-bit area, A22 must be set to VIH.
10) X can be VIH or VIL.
Command List (WP# =VIL)
Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are needed for page
program operation.
1st Bus Cycle
Setup Command for
Software Lock Release
Software Command Definition
Address
Block
Block#
DQ7
fixed 0
fixed 0
DQ6
A21
A21#
DQ5
A20
A20#
DQ4
A19
A19#
DQ3
A18
A18#
DQ2
A17
A17#
DQ1
A16
A16#
DQ0
A15
A15#
1) In the case of word mode(BYTE#=VIH) upper byte data (DQ15-DQ8) is ignored.
2) WA=Write Address, WD=Write Data
3) WA0, WAn=Write Address, WD0, WDn=Write Data. Write address and write data must be provided sequentially
from 00H to 7FH for A6-A0(word mode) and from 00H to FFH for A6-A-1(byte mode), respectively.
Page size is 128 words (128-word x 16-bit/ word mode) or Page size is 256 bytes (256-word x 8-bit/ byte mode),
and also A22-A7 (block address, page address) must be valid.
4) WA=Write Address: A22-A7 (block address, page address) must be valid.
5) BA=Block Address : A21-A12[Bank(I),Bank(VIII)], A21-A15 [Bank(II) ~ Bank(VII)]
6) Block=Block Address: A21-A15, Block#=A21#-A15#
Data
1)
Data
1)
Data
1)
(DQ0-15/DQ0-7)
60H
60H
60H
60H
60H
60H
60H
(DQ0-15/DQ0-7)
Block
6)
Block
6)
Block
6)
Block
6)
Block
6)
Block
6)
Block
6)
(DQ0-15/DQ0-7)
ACH
ACH
ACH
ACH
ACH
ACH
ACH
Word Program
Page Program
Page Buffer to Flash
Block Erase/Confirm
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Data
1)
Data
1)
(DQ0-15/DQ0-7)
Block#
6)
Block#
6)
Block#
6)
Block#
6)
Block#
6)
Block#
6)
Block#
6)
(DQ0-15/DQ0-7)
Word Program
Page Program
Page Buffer to Flash
Block Erase/Confirm
Clear Page Buffer
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
7BH
7BH
7BH
7BH
7BH
7BH
7BH
Single Data Load to Page Buffer
Flash to Page Buffer
Data
1)
Data
Data
(DQ0-15/DQ0-7)
(DQ0-15/DQ0-7)
WD
2)
WD0
3)
D0H
1)
D0H
1)
D0H
1)
(DQ0-15/DQ0-7)
Word Program
Page Program
Page Buffer to Flash
Block Erase/Confirm
Clear Page Buffer
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
A22
9)
A0-A21=X
10)
A22
9)
A0-A21=X
10)
Bank
8)
40H
41H
0EH
20H
55H
Write
Write
Write
Write
Write
WA
2)
WA0
3)
WA
4)
BA
5)
A22
9)
Write
WAn
3)
WDn
3)
A0-A21=X
10)
WA
2)
Single Data Load to Page Buffer
Write
74H
Write
WD
2)
Flash to Page Buffer
Write
F1H
Write
RA
7)
D0H
1)
Mode
Address
2nd Bus Cycle
Address
3rd Bus Cycle
Mode
Address
Mode
Address
Setup Command for
Program or Erase Operations
6th Bus Cycle
7th Bus Cycle
Setup Command for
Software Lock Release
4th Bus Cycle
5th Bus Cycle
Mode
Address
Mode
8th-134th Bus Cycles
8th-262th Bus Cycles(Byte mode)
Mode
Address
Mode
Address
Mode
Address