參數(shù)資料
型號: M5M29KE131BTP
廠商: Renesas Technology Corp.
英文描述: 134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT) CMOS FLASH MEMORY
中文描述: 134217728位(16,777,216 - Word的8位/ 8388608字由16位)的CMOS閃存
文件頁數(shù): 16/33頁
文件大?。?/td> 336K
代理商: M5M29KE131BTP
M5M29KE131BTP
Renesas LSIs
Rev.1.1_48a_bezz
16
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
-Timing measurements are made under AC waveforms for read operations.
-Typical values at Flash VCC=3.3V and Ta=25
°
C
.
Read / Write Mode (CE# control)
AC electrical characteristics
(Ta=-40 ~85
°
C and Flash VCC=3.0V~3.6V, unless otherwise noted)
-Read timing parameters during command write operations mode are the same as during read only operation mode.
-Typical values at Flash VCC=3.3V and Ta=25
°
C
.
Read / Write Mode (WE# control)
Min.
70
35
0
35
0
10
0
0
35
30
35
70
0
70
0
Typ.
Max.
tWC
tAS
tAH
tDS
tDH
tOEH
tCS
tCH
tWP
tWPH
tBS
tBH
tGHWL
tBLS
tBLH
tDAP
tDAP
tDAP
tDAE
tWHRL
tPS
tAVAV
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tELWL
tWHEH
tWLWH
tWHWL
tFL/HWH
tWHFL/H
tGHWL
tPHHWH
tQVPH
tWHRH1
tWHRH1
tWHRH1
tWHRH2
tWHRL
tPHWL
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE# Hold from WE# High
Chip Enable Setup Time
Chip Enable Hold Time
Write Pulse Width
Write Pulse Width High
Byte enable high or low set-up time
Byte enable high or low hold time
OE# Hold to WE# Low
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
Duration of Auto Program Operation(Word Mode)
Duration of Auto Program Operation(Byte Mode)
Duration of Auto Program Operation(Page Mode)
Duration of Auto Block Erase Operation
Delay Time During Internal Operation
RP# Recovery to CE# Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ms
ms
ns
ns
30
30
4
150
300
300
80
600
70
150
Symbol
Parameter
Limits
Units
Flash VCC=3.0-3.6V
Min.
70
35
0
35
0
10
0
0
35
30
35
70
0
70
0
Typ.
Max.
tWC
tAS
tAH
tDS
tDH
tOEH
tWS
tWH
tCEP
tCEPH
tBS
tBH
tGHEL
tBLS
tBLH
tDAP
tDAP
tDAP
tDAE
tEHRL
tPS
tAVAV
tAVEH
tEHAX
tDVEH
tEHDX
tEHGL
tWLEL
tEHWH
tELEH
tEHEL
tFL/HEH
tEHFL/H
tGHEL
tPHHEH
tQVPH
tEHRH1
tEHRH1
tEHRH1
tEHRH2
tEHRL
tPHEL
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE# Hold from CE# High
Write Enable Setup Time
Write Enable Hold Time
CE# Pulse Width
CE#"H" Pulse Width
Byte enable high or low set-up time
Byte enable high or low hold time
OE# Hold to CE# Low
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
Duration of Auto Program Operation(Word Mode)
Duration of Auto Program Operation(Byte Mode)
Duration of Auto Program Operation(Page Mode)
Duration of Auto Block Erase Operation
Delay Time During Internal Operation
RP# Recovery to CE# Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ms
ms
ns
ns
30
30
4
150
300
300
80
600
70
150
Symbol
Parameter
Limits
Units
Flash VCC=3.0-3.6V
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