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參數(shù)資料
| 型號(hào)： | M66252FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1152 x 8-BIT LINE MEMORY FIFO |
| 中文描述： | 1152 × 8位線記憶先進(jìn)先出 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | M66252FP |
10
MITSUBISHI
DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
Shortest read of data “n” written in cycle n
Cycle n–1 on read side should be started after end of cycle n+1 on write side
When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid.
In the figure shown below, the read of cycle n–1 is invalid.
(n)
(n + 1)
(n + 2)
(n + 3)
(n)
invalid
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
Cycle n
Cycle n – 1
Cycle n – 2
WCK
D
n
RCK
Q
n
(n – 1)
1
(n – 1)
0
(0)
1
(n)
1
(n)
0
(n – 1)
1
(0)
2
(n)
2
(n – 1)
2
(n)
1
Cycle n
1
Cycle 0
2
Cycle n
2
Cycle n
0
Cycle 0
1
Cycle n
1
WCK
D
n
RCK
Q
n
0
,
1
and
2
indicates a line value.
Longest read of data “n” written in cycle n: 1-line delay
Cycle n <1>* on read side should be started when cycle n <2>* on write is started
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over-
lap each other.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66252P | 1152 x 8-BIT LINE MEMORY FIFO |
| M66256 | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66257 | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66252P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
| M66255FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 10-BIT LINE MEMORY (FIFO) |
| M66255FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66256 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit Line Memory (FIFO) |
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