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參數(shù)資料
| 型號(hào)： | M66252FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1152 x 8-BIT LINE MEMORY FIFO |
| 中文描述： | 1152 × 8位線記憶先進(jìn)先出 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | M66252FP |
9
MITSUBISHI
DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
n-bit delay 2
(Sliding WRES and RRES at a cycle corresponding to delay length)
n-bit delay 3
(Disabling RE at a cycle corresponding to delay length)
Cycle 0(W) Cycle 1(W) Cycle 2(W)
Cycle
(n–1)(W)
Cycle n(W)
Cycle 0(R)
Cycle(n+1)(W)
Cycle 1(R)
Cycle(n+2)(W)
Cycle 2(R)
Cycle(n+3)(W)
Cycle 3(R)
t
RESS
t
RESH
t
NREH
t
RES
t
DS
t
DH
t
DS
t
DH
(0)
(1)
(2)
(n–2)
(n–1)
(n)
(n+1)
(n+2)
(n+3)
m cycles
t
AC
t
OH
HIGH-Z
(0)
(1)
(2)
(3)
Dn
Qn
RE
WRES
RRES
WCK
RCK
WE, RE=“L”
m
≥
3
Cycle 0(W) Cycle 1(W) Cycle 2(W)
Cycle
(n–1)(W)
Cycle n(W)
Cycle 0(R)
Cycle(n+1)(W)
Cycle 1(R)
Cycle(n+2)(W)
Cycle 2(R)
Cycle(n+3)(W)
Cycle 3(R)
t
RESS
t
RESH
t
RESS
t
RESH
t
DS
t
DH
t
DH
t
DS
(0)
(1)
(2)
(n–2)
(n–1)
(n)
(n+1)
(n+2)
(n+3)
(0)
(1)
(3)
(2)
m cycles
t
AC
t
DH
Qn
Dn
RRES
WRES
WCK
RCK
WE, RE=“L”
m
≥
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66252P | 1152 x 8-BIT LINE MEMORY FIFO |
| M66256 | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66257 | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66252P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
| M66255FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 10-BIT LINE MEMORY (FIFO) |
| M66255FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66256 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit Line Memory (FIFO) |
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