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參數(shù)資料
| 型號： | M66252FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1152 x 8-BIT LINE MEMORY FIFO |
| 中文描述： | 1152 × 8位線記憶先進先出 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | M66252FP |
8
MITSUBISHI
DIGITAL ASSP
M66252P/FP
1152 x 8-BIT LINE MEMORY (FIFO)
VARIABLE-LENGTH DELAY BITS
1-line (1152-bit) delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from
memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
n-bit delay 1
(Making a reset at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle
(n–2)
Cycle
(n–1)
Cycle 0’
Cycle 1’
Cycle 2’
Cycle 3’
t
RESS
t
RESH
t
RESS
t
RESH
t
DS
t
DS
t
DH
t
DH
(1)
(0)
(2)
(n–3)
(n–2)
(n–1)
(0’)
(1’)
(2’)
(3’)
(0)
(1)
(2)
(3)
WE, RE=“L”
m
≥
3
m cycles
t
AC
t
OH
Qn
Dn
WRES
RRES
WCK
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle
1150
Cycle
1151
Cycle 0’
Cycle 1’
Cycle 2’
t
RESS
t
RESH
t
DS
t
DH
t
DS
t
DH
(0)
(1)
(2)
(1149)
(1150)
(1151)
(0’)
(1’)
(2’)
1152 cycles
t
AC
t
OH
(0)
(1)
(2)
Dn
Qn
WRES
RRES
WCK
RCK
WE, RE=“L”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M66252P | 1152 x 8-BIT LINE MEMORY FIFO |
| M66256 | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 5120 x 8-BIT LINE MEMORY (FIFO) |
| M66257 | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
| M66257FP | 5120 x 8-BIT x 2 LINE MEMORY (FIFO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66252P | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1152 x 8-BIT LINE MEMORY FIFO |
| M66255FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8192 x 10-BIT LINE MEMORY (FIFO) |
| M66255FP(#TB0T) | 制造商:Renesas Electronics Corporation 功能描述: |
| M66256 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:5120 x 8-BIT LINE MEMORY (FIFO) |
| M66256FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:5120 × 8-Bit Line Memory (FIFO) |
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