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參數(shù)資料
| 型號： | M66271FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | OPERATION PANEL CONTROLLER |
| 中文描述： | 操作面板控制器 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 289K |
| 代理商： | M66271FP |
OPERATION PANEL CONTROLLER
M66271FP
MITSUBISHI <DIGITAL ASSP>
SWITCHING CHARACTERISTICS (V
DD
=5V
±
10%, Ta=0 – +70C)
t
a(RD-D)
t
dis(IOCS-D)
t
dis(MCS-D)
70
ns
t
dis(RD-D)
t
pHL(MCS-WAIT)
20
ns
t
pd(OSC-CP)
40
ns
t
pLH(OSC-LP)
t
pHL(OSC-LP)
40
ns
t
a(UD)
40
ns
t
pLH(OSC-FLM)
t
pHL(OSC-FLM)
40
ns
t
pd(OSC-M)
t
pLH(OSC-LE)
t
pHL(OSC-LE)
40
ns
40
ns
t
pHL(WR-WAIT)
t
pHL(RD-WAIT)
t
pLH(CLK-WAIT)
20
ns
40
ns
C
L
=50pF
t
a(IOCS-D)
t
a(MCS-D)
t
pd(D-WAIT)
0
ns
Symbol
Parameter
Test
condition
Limits
Typ.
Min.
Max.
Unit
RD data access time
Output disable time after IOCS
Output disable time after MCS
IOCS data access time
MCS data access time
Output disable time after RD
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
WAIT output propagation time after MPUCLK
CP output propagation time after OSC
LP output propagation time after OSC
UD access time
FLM output propagation time after OSC
M output propagation time after OSC
LCDENB output propagation time after OSC
Data definite time before cancelling WAIT
TIMING REQUIREMENTS (V
DD
=5V
±
10%, Ta=0 – +70C)
(1) Accessing to control register
t
W(LWR)
t
su(D-IOCS)
70
ns
t
su(D-LWR)
t
h(IOCS-D)
0
ns
t
h(LWR-D)
t
su(A-IOCS)
t
su(A-LWR)
t
su(A-RD)
15
ns
15
ns
t
h(LWR-A)
t
h(RD-A)
15
ns
t
W(IOCS)
t
h(IOCS-A)
Symbol
Parameter
Test
condition
Limits
Typ.
Unit
Min.
Max.
LWR pulse width
Data set up time before falling edge of IOCS
IOCS pulse width
Data set up time before falling edge of LWR
Data hold time after rising edge of IOCS
Data hold time after rising edge of LWR
Address set up time before falling edge of IOCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
Address hold time after rising edge of IOCS
(2) Accessing to VRAM
t
W(WR)
70
ns
t
su(D-WR)
0
ns
t
h(WR-D)
15
ns
t
su(A-MCS)
t
su(A-WR)
t
su(A-RD)
15
ns
t
h(WR-A)
t
h(RD-A)
15
ns
t
W(MCS)
t
su(D-MCS)
t
h(MCS-D)
t
h(MCS-A)
Symbol
Parameter
Test
condition
Limits
Typ.
Unit
Min.
Max.
WR pulse width
MCS pulse width
Data set up time before falling edge of WR
Data set up time before falling edge of MCS
Data hold time after rising edge of WR
Data hold time after rising edge of MCS
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
Address hold time after rising edge of WR
Address hold time after rising edge of RD
Address hold time after rising edge of MCS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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