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參數(shù)資料
| 型號： | M66271FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | OPERATION PANEL CONTROLLER |
| 中文描述： | 操作面板控制器 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 289K |
| 代理商： | M66271FP |
OPERATION PANEL CONTROLLER
M66271FP
MITSUBISHI <DIGITAL ASSP>
(5) Write to VRAM ( RD = "H" )
Term of cycle steal access
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
tWH(CLK)
tC(CLK)
tWL(CLK)
LWR
(+HWR)
A<13:0>
(+
BHE)
th(WR-D)
tsu(D-WR)
tsu(D-MCS)
tsu(A-MCS)
tsu(A-WR)
th(WR-A)
tw(WR)
tw(MCS)
th(MCS-A)
th(MCS-D)
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
tpLH(CLK-WAIT)
Address is established
Data input is established
(6) Read from VRAM ( LWR,HWR = "H" )
Term of cycle steal access
MPUCLK
MCS
WAIT
D<7:0>
(D<15:0>)
tWH(CLK)
tC(CLK)
tWL(CLK)
RD
A<13:0>
tdis(RD-D)
ta(RD-D)
ta(MCS-D)
tsu(A-MCS)
tsu(A-RD)
th(RD-A)
th(MCS-A)
tdis(MCS-D)
tpHL(MCS-WAIT)
tpHL(RD-WAIT)
tpLH(CLK-WAIT)
tpd(D-WAIT)
Data output is established
Address is established
Note 3: Reading/writing operation for VRAM during cycle steal needs 1tc(Internal) in best case or 3tc(Internal) in worst
case,according to the condition of the internal cycle steal at starting access requested from MPU.
tc(Internal) = Clock cycle time after setting division of OSC1.
Data output D in reading is established before changing WAIT to "H".
4: Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access,
and by the input signal of first change to "H" in ending access.
5: Always once return MCS,LWR(+HWR) or RD to "H" after canceling WAIT output.
In case of latching "L",as don't output next WAIT,this is cause of error action.
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