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參數(shù)資料
| 型號(hào)： | M66271FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | OPERATION PANEL CONTROLLER |
| 中文描述： | 操作面板控制器 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 289K |
| 代理商： | M66271FP |
OPERATION PANEL CONTROLLER
M66271FP
MITSUBISHI <DIGITAL ASSP>
Note: Clock frequency of OSC1 input is less than fmax=20MHz.
Limit of OSC clock for the internal operation is fmax=10MHz.
When OSC1 is more than 10MHz from external input, set OSC clock
up to 10MHz by using division of OSCC register.
Division is set with rising edge of OSC1 input.
(3) Clock and accessing to LCD display
1/n =Division of OSC1
LPW=Setting value of LPW register
t
C(CLK)
50
ns
t
WH(CLK)
t
WL(CLK)
ns
ns
ns
ns
ns
ns
t
C(OSC)
t
WH(OSC)
t
WL(OSC)
t
C(CP)
t
WH(CP)
t
WL(CP)
t
W(FLM)
P.G
DUT
Input
V
DD
Outputs
except for
D<15:0>
50
C
L
V
DD
R
L
=1K
R
L
=1K
SW1
SW2
D<15:0>
C
L
V
SS
Parameter
t
dis
(LZ)
t
dis
(HZ)
t
a
(ZL)
t
a
(ZH)
SW1
Closed
Open
SW2
Open
Closed
Open
Input pulse level : 0 – 3V
Input pulse rise/fall time : tr,tf=3ns
Input decision voltage : 1.5V
Output decision voltage : V
DD
/2
(However,tdis(LZ) is 10% of output amplitude and tdis
(HZ) is 90% of that for dezision.)
Load capacity CL include float capacity of connection
and input capacity of probe.
(1)
(2)
Symbol
Parameter
Test condition
Limits
Typ.
Unit
MIn.
Max.
MPUCLK cycle time
MPUCLK "L" pulse width
OSC cycle time
OSC "H" pulse width
OSC "L" pulse width
CP cycle time
CP "H" pulse width
CP "L" pulse width
FLM pulse width
2
t
C(CLK)
50
(note)
2
t
C(OSC)
(1/n)
t
C(OSC)
2
(1/n)
t
C(OSC)
2
t
C(OSC)
LPW
(1/n)
Test circuit
Closed
Open
Closed
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