Electrical Specifications
M68HC12B Family Data Sheet, Rev. 9.1
316
Freescale Semiconductor
19.12.2 Example V
FP
Protection Circuitry
Figure 19-2
shows an example of a circuit which, if properly implemented, can maintain the appropriate
voltage levels on the V
FP
pin. This section outlines the design for this circuit, what each component is
intended to do, and some design considerations when designing V
FP
pin protection.
Figure 19-2. V
FP
Supply Circuit
The general idea of this circuit implementation is to supply V
FP
from a dc-dc converter. This dc-dc
converter, like most, provides a shutdown feature which allows the converter’s output to be shut off. When
the SHDN pin on the converter is pulled high, as the 10-k
pullup resistor (R1) does, the output V
Out
is
shorted to the V
DD
supply. This requires that the programming and erasing routines assert a port pin on
the MCU to turn on the converter and supply the 12-volt programming voltage during the programming or
erasing cycle. Simple programming and erasing routines, such as those shown earlier in this application
note, will no longer suffice.
By implementing this solution, V
FP
is tied to V
DD
on power-up and power-down, ensuring that they rise
and fall together. Capacitors C5 and C6 are the normal decoupling capacitors on the V
DD
supply lines.
C3 is used to reduce electromagnetic interference (EMI) in the circuit. If C3 is too large, V
FP
will not be
allowed to fall with V
DD
, potentially causing data corruption in the FLASH array. (Refer to
Figure 19-3
.)
C4 is where the dc-dc converter stores charge to supply V
Out
to the target device. The supply must be
able to source approximately 30 mA of current for at least 20
μ
s (based on programming cycle
requirements) and 4 mA of current for at least 10 ms (based on erase cycle requirements).
A certain degree of experimentation might be required when selecting C4 and C3. When trying different
capacitor values, always monitor the effects on V
FP
decay during power-down and current supplied to the
V
FP
pin.
R1 must be no larger than 10 k
, to make certain that the SHDN pin on the dc-dc converter is never
allowed to fall below V
DD
unless the output pin of the microcontroller is driven low. The external pullup
ensures this behavior, no matter what port pin is used on the microcontroller or what the internal structure
of that pin looks like. Without a strong enough pullup resistor on R1, the voltage on the SHDN pin might
drop during a reset event, causing the dc-dc converter to activate and begin driving the voltage on V
Out
to begin to rise to 12 volts. This would result in data corruption in the FLASH.
V
DD
C1+
C1 –
C2+
C2–
5
2
1
4
3
220 nF
220 nF
7
GND
SHDN
V
OUT
ST662A
6
8
C4
10
μ
F
C3
1–100 nF
R1 10 k
V
FP
SHUTDOWN
C5
10
μ
F
C6
100 nF
V
DD
V
FP
I/O
V
SS
V
DD