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參數(shù)資料
| 型號(hào)： | M69AW024B |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Mbit (1M x16) 3V Asynchronous PSRAM |
| 中文描述： | 16兆位（1米× 16）3V的異步移動(dòng)存儲(chǔ)芯片 |
| 文件頁(yè)數(shù)： | 9/29頁(yè) |
| 文件大?。?/td> | 429K |
| 代理商： | M69AW024B |
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M69AW024B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see
Table 2.
).
Power On Sequence
Because the internal control logic of the
M69AW024B needs to be initialized, the following
power-on procedure must be followed before the
memory is used:
–
Apply power and wait for V
CC
to stabilize
–
Wait 400μs while driving both Chip Enable
signals (E1 and E2) High
–
Activate the memory by driving Chip
Enable (E1) Low.
Read Mode
The device is in Read mode when:
–
Write Enable (W) is High and
–
Output Enable (G) Low and
–
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (t
ELQV
, t
GLQV
or t
BLQV
) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during t
ELQX
, t
GLQX
and t
BLQX
, but data will always
be valid during t
AVQV
.
Write Mode
The device is in Write mode when
–
Write Enable (W) is Low and
–
Chip Enable (E1) is Low and
–
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High)
one of Upper Byte Enable (UB) or Lower
Byte Enable (LB) is Low, while the other is
High.
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (t
AVWL
or t
AVEL
or t
AVBL
).
The Write cycle is terminated by the earlier of a ris-
ing edge on Write Enable (W) or Chip Enable (E1).
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) or Lower Byte Enable (LB) is Low), then
Write Enable (W) will return the outputs to high im-
pedance within t
WLQZ
of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
DVWH
before
the rising edge of Write Enable (W), or for t
DVEH
before the rising edge of Chip Enable (E1), which-
ever occurs first, and remain valid for t
WHDX
, t
EHDX
Standby Mode
The device is in Standby mode when:
–
Chip Enable (E1) is High and
–
Chip Enable (E2) is High.
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, I
SB
, is reduced, and the data
remains valid.
Deep Power-down Mode
The device is in Deep Power-down mode when:
–
Chip Enable (E2 is Low).
–
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M69AW024BE | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Mbit (1M x16) 3V Asynchronous PSRAM |
| M69AW024BE60ZB1F | 制造商:Micron Technology Inc 功能描述:16MB 3V WIRELESS NOR DEVICE - Tape and Reel |
| M69AW024BE60ZB8F | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 16 Mbit 1M x16 3V Async P靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| M69AW024BL60ZB8T | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 16 MBIT (1M X16) 3V Asynch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| M69AW024BL70ZB8T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:16 Mbit (1M x16) 3V Asynchronous PSRAM |
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