參數(shù)資料
型號: M7020R-066ZA1T
廠商: 意法半導(dǎo)體
英文描述: 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述: 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁數(shù): 136/150頁
文件大小: 996K
代理商: M7020R-066ZA1T
M7020R
136/150
SRAM WRITE with a Table of One Device
SRAM WRITE enables WRITE access to the off-
chip SRAM that contains associative data. The la-
tency from the second cycle of the WRITE Instruc-
tion to the address appearing on the SRAM Bus is
the same as the latency of the SEARCH Instruc-
tion, and will depend on the TLSZ value parameter
programmed in the device configuration register.
The following explains the SRAM WRITE opera-
tion accomplished with a table of only one device
of the following parameters: TLSZ = 00, HLAT =
000, LRAM = 1, and LDEV = 1. Figure 100, page
137 shows the timing diagram.
For the following description the selected device
refers to the only device in the table as it is the only
device that will be accessed.
Cycle 1A:
The host ASIC applies the WRITE In-
struction on CMD[1:0] using CMDV = 1. The DQ
Bus supplies the address with DQ[20:19] set to
'10' to select the SRAM address. The host ASIC
selects the device for which the ID[4:0] matches
the DQ[25:21] lines. The host ASIC also sup-
plies SADR[21:20] on CMD[8:7] in this cycle.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 1B:
The host ASIC continues to apply the
WRITE
Instruction
CMDV = 1. The DQ Bus supplies the address
with DQ[20:19] set to '10' to select the SRAM
address.
Note:
CMD[2] must be set to '0' for SRAM
WRITE because Burst WRITEs into the SRAM
are not supported.
Cycle 2:
The host ASIC continues to drive
DQ[67:0]. The data in this cycle is not used by
the M7020R device.
Cycle 3:
The host ASIC continues to drive
DQ[67:0]. The data in this cycle is not used by
the M7020R device.
At the end of Cycle 3, a new command can begin.
The WRITE is a pipelined operation. The WRITE
Cycle appears at the SRAM Bus, however, with
the same latency as that of a SEARCH Instruction,
as measured from the second cycle of the WRITE
command.
on
CMD[1:0],
using
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參數(shù)描述
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