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參數(shù)資料
| 型號(hào)： | M7020R-066ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎 |
| 文件頁(yè)數(shù)： | 47/150頁(yè) |
| 文件大?。?/td> | 996K |
| 代理商： | M7020R-066ZA1T |
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M7020R
The following is the sequence of operation for a
single 68-bit SEARCH command (also refer to
Command Codes, page 29).
–
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair for use in
this SEARCH operation. CMD[8:7] signals must
be driven with the same bits that will be driven
on SADR[21:20] by this device if it has a hit.
DQ[67:0] must be driven with the 68-bit data to
be compared. The CMD[2] signal must be driv-
en to a logic '0.'
–
Cycle B:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
('10') on CMD[1:0]. CMD[5:2] must be driven by
the index of the comparand register pair for stor-
ing the 136-bit word presented on the DQ Bus
during Cycles A and B. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and the Hit Flag (see SEARCH-Successful
Registers (SSR[0:7]), page 23). The DQ[67:0]
continues to carry the 68-bit data to be com-
pared.
Note:
For 68-bit searches, the host ASIC must
supply the same 68-bit data on DQ[67:0] during
both Cycles A and B. The even and odd pair of
GMRs selected for the comparison must be pro-
grammed with the same value.
The logical 68-bit SEARCH operation is shown in
Figure 29, page 50. The entire table (31 devices of
68-bit entries) is compared to a 68-bit word K (pre-
sented on the DQ Bus in both Cycles A and B of
the command) using the GMR and the local mask
bits. The effective GMR is the 68-bit word speci-
fied by the identical value in both even and odd
GMR pairs in each of the eight devices and select-
ed by the GMR Index in the command’s Cycle A.
The 68-bit word K (presented on the DQ Bus in
both Cycles A and B of the command) is also
stored in both even and odd comparand register
pairs in each of the eight devices and selected by
the Comparand Register Index in command’s Cy-
cle B. In the x68 configuration, the even com-
parand register can be subsequently used by the
LEARN command only in the first non-full device.
The word K (presented on the DQ Bus in both Cy-
cles A and B of the command) is compared with
each entry in the table starting at location “0.” The
first matching entry’s location address, “L,” is the
winning address that is driven as part of the SRAM
address on the SADR[21:0] lines (see SRAM AD-
DRESSING, page 126). The global winning device
will drive the bus in a specific cycle. On global miss
cycles the device with LRAM = 1 and LDEV = 1 will
be the default driver for such missed cycles.
The SEARCH command is a pipelined operation
and executes a search at half the rate of the fre-
quency of CLK2X for 68-bit searches in x68-con-
figured tables. The latency of SADR, CE_L,
ALE_L, WE_L, SSV, and SSF from the 68-bit
SEARCH command cycle (two CLK2X cycles) is
shown in Table 31, page 62.
For up to 31 devices in the table (TLSZ = 10),
search latency from command to SRAM access
cycle is 6. In addition, SSV and SSF shift further to
the right for different values of HLAT, as specified
in Table 32, page 62.
The 68-bit SEARCH operation is pipelined and ex-
ecutes as follows:
– Four cycles from the SEARCH command, each
of the devices knows the outcome internal to it
for that operation;
– In the fifth cycle after the SEARCH command,
the devices in a block arbitrate for a winner
amongst them (a “block” being defined as less
than or equal to eight devices resolving the win-
ner within them using the LHI[6:0] and LHO[1:0]
signalling mechanism);
– In the sixth cycle after the SEARCH command,
the blocks (of devices) resolve the winning block
through the BHI[2:0] and BHO[2:0] signalling
mechanism. The winning device within the win-
ning block is the global winning device for a
SEARCH operation.
Table 30. Hit/Miss Assumption
Search Number
1
2
3
4
Block 0
Miss
Miss
Miss
Miss
Block 1
Miss
Miss
Hit
Miss
Block 2
Miss
Hit
Hit
Miss
Block 3
Hit
Hit
Miss
Miss
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7020R-083ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE |
| M702-230442 | 功能描述:火線接頭 IEEE 1394 SMT 4P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M702-230642 | 功能描述:火線接頭 IEEE 1394 SMT 6P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M7023 | 制造商:Tamura Corporation of America 功能描述: |
| M7027 | 功能描述:數(shù)字萬(wàn)用表 Dual Display Multime 0.3% Accuracy RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
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