參數(shù)資料
型號： M7020R-066ZA1T
廠商： 意法半導(dǎo)體
英文描述： 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述： 32K的× 68位進入網(wǎng)絡(luò)搜索引擎
文件頁數(shù)： 32/150頁
文件大小： 996K
代理商： M7020R-066ZA1T
M7020R
32/150
Table 18. READ Command Parameters
Table 19. Data and Mask Array, SRAM Read Address Format
Note: 1.
“|” stands for Logical OR operation. “{ }” stands for concatenation operator.
CMD Parameter
CMD[2]
Read Command
Description
0
Single Read
Reads a single location of the data array, mask array, external SRAM,
or device registers. All access information is applied on the DQ Bus.
1
Burst Read
Reads a block of locations from the data array or mask array as a
burst.
The internal register (RBURADR) specifies the starting address and
the length of the data transfer from the data array or mask array, and it
auto-increments the address for each access.
All other access information is applied on the DQ Bus.
Note:
The device registers and external SRAM can only be read in
single-read mode.
DQ
[67:30]
DQ
[29]
DQ
[28:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:15]
DQ
[14:0]
Reserved
0: Direct
1: Indirect
Successful SEARCH
Register Index
(Applicable if DQ[29]
is indirect)
ID
00: Data
Array
Reserved
If DQ[29] is ’0,’ this field carries
address of data array location.
If DQ[29] is ’1,’ the successful
search register ID (SSRI)
specified on DQ[28:26] supplies
the address of the data array
location:
{SSR[14:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}
(1)
Reserved
0: Direct
1: Indirect
Successful SEARCH
Register Index
(Applicable if DQ[29]
is indirect)
ID
01: Mask
Array
Reserved
If DQ[29] is ’0,’ this field carries
address of mask array location.
If DQ[29] is ’1,’ the successful
search register ID (SSRI)
specified on DQ[28:26] supplies
the address of the mask array
location:
{SSR[14:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}
(1)
Reserved
0: Direct
1: Indirect
Successful SEARCH
Register Index
(Applicable if DQ[29]
is indirect)
ID
10:
External
SRAM
Reserved
If DQ[29] is ’0,’ this field carries
address of SRAM location.
If DQ[29] is ’1,’ the successful
search register ID (SSRI)
specified on DQ[28:26] supplies
the address of the SRAM
location:
{SSR[14:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}
(1)
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