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| 型號(hào)： | M7020R-066ZA1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎 |
| 文件頁(yè)數(shù)： | 24/150頁(yè) |
| 文件大?。?/td> | 996K |
| 代理商： | M7020R-066ZA1T |
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M7020R
24/150
The Command Register
Table 10. Command Register Field Descriptions
Field
Range
Initial Value
Description
SRST
[0]
0
Software Reset.
If ’1,’ this bit resets the device, with the same effect
as the hardware reset. Internally, it generates a reset pulse lasting for
eight CLK cycles. This bit automatically resets to a ’0’ the reset cycle
has completed.
DEVE
[1]
0
Device Enable.
If ’0,’ it keeps the SRAM Bus (SADR, WE_L, CE_L,
OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and
forces the cascade interface output signals LHO[1:0] and BHO[2:0] to
’0.’ It also keeps the DQ Bus in input mode. The purpose of this bit is
to make sure that there are no bus contentions when the devices
power up in the system.
TLSZ
[3:2]
01
Table Size.
The host ASIC must program this field to configure the
chips into a table of a certain size. This field affects the pipeline
latency of the SEARCH and LEARN operations as well as the READ
and WRITE accesses to the SRAM (SADR[21:0], CE_L, OE_L,
WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search
latency stays constant.
TLSZ
[3:2]
01
Latency in #
of CLK Cycles
00: 1 device
4
01: 2-8 devices
5
10: 9-31 devices
6
11: Reserved
HLAT
[6:4]
000
Latency of Hit Signals.
This field adds latency to the SSF and SSV
signals during SEARCH, and ACK signal during SRAM READ access
by the following number of CLK cycles.
000: 0
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7
LDEV
[7]
0
Last Device in the Cascade.
When set, this device is the last device
on the SRAM bus in the depth-cascaded table and is the default driver
for the SSF and SSV signals.
In the event of a SEARCH failure, the device with this bit set drives the
hit signals as follows:
SSF = 0, SSV = 1
During non-SEARCH cycles, the device with this bit set drives the
signals as follows:
SSF = 0, SSV = 0
LRAM
[8]
0
Last device on this SRAM Bus.
When set, this device is the last
device on this SRAM bus in the depth-cascaded table and is the
default driver for the SADR, CE_L, WE_L, and ALE_L signals. In
cycles where no M7020R device in a depth-cascaded table drives
these signals, this device drives the signals as follows:
SADR = 3FFFFF,
CE_L = 1
WE_L = 1
ALE_L = 1
OE_L is always driven by the device for which this bit is set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7020R-083ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE |
| M702-230442 | 功能描述:火線接頭 IEEE 1394 SMT 4P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M702-230642 | 功能描述:火線接頭 IEEE 1394 SMT 6P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle |
| M7023 | 制造商:Tamura Corporation of America 功能描述: |
| M7027 | 功能描述:數(shù)字萬(wàn)用表 Dual Display Multime 0.3% Accuracy RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
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