SPI/I2C UART with 128-Word FIFOs Multidrop Mode In multidrop mode, also known as" />
參數(shù)資料
型號(hào): MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/52頁(yè)
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Multidrop Mode
In multidrop mode, also known as 9-bit mode, the word
length is 8 bits and a 9th bit is used for distinguishing
between an address and a data word. Multidrop mode is
enabled through MODE2[6]: MultiDrop. Parity checking
is disabled and an SpclCharInt[5]: MultiDropInt interrupt
is generated when an address (9th bit set) is received.
It is up to the host processor to filter out the data intend-
ed for its address. Alternatively, the auto data-filtering
mode can be used to automatically filter out the data
intended for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop Mode
In multidrop mode, the MAX3107 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
values and GPIO hardware inputs. Use either XOFF2
or XOFF2[7:4] in combination with GPIO_ to define the
address.
Enable multidrop mode by setting MODE2[6]: MultiDrop
to 1 and enable auto data filtering by setting MODE2[4]:
SpecialChr to 1.
When using register bits in combination with GPIO_ to
define the address, the MSB of the address is written to
XOFF2[7:4] register bits, while the LSBs of the address
are defined through the GPIOs. To enable this mode,
set FlowCtrl[2]: GPIAddr, MODE2[4]: SpecialChr, and
MODE2[6]: MultiDrop to 1. GPIO_ is automatically read
when FlowCtrl[2]: GPIAddr is set to 1, and the address
is updated on logic changes at GPIO_.
In the auto data-filtering mode, the MAX3107 auto-
matically accepts data that is meant for its address and
places this into the receive FIFO, while it discards data
that is not meant for its address. The received address
word is not put into the FIFO.
Auto Transceiver Direction Control
In some half-duplex communication systems, the trans-
ceiver’s transmitter must be turned off when data is
being received so as not to load the bus. This is the
case in half-duplex RS-485 communication. Similarly
in full-duplex multidrop communication, like RS-485 or
RS-422/V.11, only one transmitter can be enabled at any
one time and the others must be disabled. The MAX3107
can automatically enable/disable a transceiver’s trans-
mitter and/or receiver. This relieves the host processor
of this time-critical task.
The RTS/CLKOUT output is used to control the transceiv-
ers’ transmit enable input and is automatically set high
when the MAX3107’s transmitter starts transmission.
This occurs as soon as data is present in the transmit
FIFO. Auto transceiver direction control is enabled
through MODE1[4]: TrnscvCtrl. Figure 9 shows a typical
MAX3107 connection in a RS-485 application.
The RTS/CLKOUT output can be set high in advance
of TX transmission by a programmable time period
called the setup time (Figure 10). The setup time is pro-
grammed through HDplxDelay[7:4]. Similarly, the RTS/
CLKOUT signal can be held high for a programmable
period after the transmitter has completed transmission.
The hold time is programmed through HDplxDelay[3:0].
Figure 9. Auto Transceiver Direction Control
MAX3107
MAX13431
TRANSMITTER
TX
B
A
D
RTS/CLKOUT
RX
TxFIFO
RECEIVER
AUTO
TRANSCEIVER
CONTROL
RxFIFO
DI
RO
RE
DE
R
Maxim Integrated
19
MAX3107
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