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參數(shù)資料
| 型號： | MAX3107EAG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SPI/I2C 128 FIFO 24SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 特點(diǎn)： | 內(nèi)部振蕩器 |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.35 V ~ 3.6 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MAX3107EAG+TDKR |
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SPI/I2C UART with 128-Word FIFOs
Detailed Description
The MAX3107 UART is a bridge between an SPI/
MICROWIRE or I2C microprocessor bus and an
asynchronous serial-data communication link, such as
RS-485, RS-232, or IrDA. The MAX3107 contains an
advanced UART, a fractional baud-rate generator, and
four GPIOs. The MAX3107 is configured and monitored,
and data is written and read from 8-bit registers through
SPI or I2C. These registers are organized by related
function as shown in the Register Map.
The host controller loads data into the Transmit Holding
register (THR) through SPI or I2C. This data is automati-
cally pushed into the transmit FIFO and sent out at TX.
The MAX3107 adds START, STOP, and parity bits to
the data and sends the data out at the selected baud
rate. The clock configuration registers determine the
baud rate, clock source selection, and clock frequency
prescaling.
The receiver in the MAX3107 detects a START bit as a
high-to-low RX transition. An internal clock samples this
data. The received data is automatically placed in the
receive FIFO and can then be read out of the RxFIFO
through the RHR.
Register Set
The MAX3107 has a flat register structure without shad-
ow registers. The registers are 8 bits wide. The MAX3107
registers have some similarities to the 16C550 registers.
Receive and Transmit FIFOs
The UART’s receiver and the transmitter each have a
128-word deep FIFO, reducing the intervals that the host
processor needs to dedicate for high-speed, high-vol-
ume data transfer. As the data rates of the asynchronous
RX, TX interfaces increase and get closer to those of the
host controller’s SPI/I2C data rates, UART management
and flow control can make up a significant portion of the
host’s activity. By increasing FIFO size, the host is inter-
rupted less often and can utilize SPI/I2C burst data block
transfers to/from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trig-
ger levels are programmed through FIFOTrgLvl with a
resolution of eight FIFO locations. When a receive FIFO
trigger is generated, the host knows that the receive
FIFO has a defined number of words waiting to be read
out or that a known number of vacant FIFO locations are
available and ready to be filled. The transmit FIFO trig-
ger generates an interrupt when the transmit FIFO level
is above the programmed trigger level. The host then
knows to throttle data writing to the transmit FIFO.
The host can read out the number of words present in each
of the FIFOs through the TxFIFOLvl and RxFIFOLvl registers.
Transmitter Operation
Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words that
are written to it through THR.
The current number of words in the TxFIFO can be read
out through the TxFIFOLvl register. The transmit FIFO
can be programmed to generate an interrupt when a
programmed number of words are present in the TxFIFO
through the FIFOTrgLvl register. The TxFIFO interrupt
trigger level is selectable through FIFOTrgLvl[3:0]. When
the transmit FIFO fill level reaches the programmed trig-
ger level, the ISR[4] interrupt is set.
The transmit FIFO is empty when ISR[5]: TxEmtyInt is set.
ISR[5] turns high when the transmitter starts transmit-
ting the last word in the TxFIFO. Hence, the transmitter
is completely empty after ISR[5] is set with an addi-
tional delay equal to the length of a complete character
(including START, parity, and STOP bits).
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst.
Figure 3. Transmit FIFO Signals
MICROWIRE is a trademark of National Semiconductor Corp.
CURRENT FILL LEVEL
TRANSMITTER
TX
TRANSMIT FIFO
FIFOTrgLvl[3:0]
TRIGGER
ISR[4]
THR
DATA FROM SPI/I2C INTERFACE
128
3
2
1
LEVEL
TxFIFOLvl
EMPTY
ISR[5]
Maxim Integrated
15
MAX3107
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| MAX3107ETG/V+ | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG/V+T | 功能描述:UART 接口集成電路 SPI/IC UART with 128-Word FIFOs and Internal Oscillator RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG+ | 功能描述:UART 接口集成電路 SPI/I2C Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107ETG+T | 功能描述:UART 接口集成電路 SPI/I2C Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX3107EVKIT+ | 功能描述:UART 接口集成電路 UART with integrated Oscillator RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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