SPI/I2C UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (continued)
參數(shù)資料
型號(hào): MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 52/52頁(yè)
文件大小: 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
AC ELECTRICAL CHARACTERISTICS (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.) (Note 2)
Note 2: All devices are production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Not production tested. Guaranteed by design.
Note 4: When V18 is powered by an external voltage regulator, the external power supply must have current capability above or
equal to I18.
Note 5: CB is the total capacitance of either the clock or data line of the synchronous bus in pF.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Data Setup Time
tSU:DAT
Standard mode
250
ns
Fast mode
100
Setup Time for Repeated START
(Sr) Condition
tSU:STA
Standard mode
4.7
F
s
Fast mode
0.6
Rise Time of SDA and SCL
Signals Receiving
tR
Standard mode (0.3 x VL to 0.7 x VL)
(Note 5)
20 +
0.1CB
1000
ns
Fast mode (0.3 x VL to 0.7 x VL) (Note 5)
20 +
0.1CB
300
Fall Time of SDA and SCL
Signals
tF
Standard mode (0.7 x VL to 0.3 x VL)
(Note 5)
20 +
0.1CB
300
ns
Fast mode (0.7 x VL to 0.3 x VL) (Note 5)
20 +
0.1CB
300
Setup Time for STOP (P)
Condition
tSU:STO
Standard mode
4.7
F
s
Fast mode
0.6
Capacitive Load for SDA and
SCL (Note 3)
CB
Standard mode
400
pF
Fast mode
400
I/O Capacitance (SCL, SDA)
CI/O
10
pF
Pulse Width of Spike
Suppressed
tSP
50
ns
SPI BUS: TIMING CHARACTERISTICS (see Figure 2)
SCLK Clock Period
tCH+CL
38.4
ns
SCLK Pulse-Width High
tCH
16
ns
SCLK Pulse-Width Low
tCL
16
ns
CS Fall to SCLK Rise Time
tCSS
0
ns
DIN Hold Time
tDH
3
ns
DIN Setup Time
tDS
5
ns
Output Data Propagation Delay
tDO
20
ns
DOUT Rise and Fall Times
tFT
10
ns
CS Hold Time
tCSH
32
ns
Maxim Integrated
9
MAX3107
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