SPI/I2C UART with 128-Word FIFOs Bits 7 and 6: PLLFactor[1:0] The two PLLFactor[" />
參數(shù)資料
型號(hào): MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 36/52頁(yè)
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bits 7 and 6: PLLFactor[1:0]
The two PLLFactor[1:0] bits allow programming the PLL’s multiplication factor. The input and output frequencies of the
PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].
Bits 5–0: PreDiv[5:0]
The six PreDiv[5:0] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen such that the
output frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4. The
input frequency of XIN is fCLK; fPLLIN = fCLK/PreDiv (Figure 4). PreDiv is an integer that must be in the range of 1 to 63.
PLLConfig—PLL Configuration Register
Table 4. PLLFactor[1:0] Selection Guide
Figure 14. PLL Signal Path
PREDIVIDER
fCLK
PLL
fPLLIN
fREF
FRACTIONAL
BAUD-RATE
GENERATOR
ADDRESS:
0x1A
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
PLLFactor1
PLLFactor0
PreDiv5
PreDiv4
PreDiv3
PreDiv2
PreDiv1
PreDiv0
RESET
0
1
PLLFactor1
PLLFactor0
MULTIPLICATION
FACTOR
fPLLIN
fREF
MIN
MAX
MIN
MAX
0
6
500kHz
800kHz
3MHz
4.8MHz
0
1
48
850kHz
1.2MHz
40.8MHz
56MHz
1
0
96
425kHz
1MHz
40.8MHz
96MHz
1
144
390kHz
667kHz
56MHz
96MHz
Maxim Integrated
41
MAX3107
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