SPI/I2C UART with 128-Word FIFOs Pin Descriptions (continued) PIN NAME FUNCTION " />
參數資料
型號: MAX3107EAG+T
廠商: Maxim Integrated Products
文件頁數: 5/52頁
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
特點: 內部振蕩器
通道數: 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 24-SSOP
包裝: 標準包裝
其它名稱: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Pin Descriptions (continued)
PIN
NAME
FUNCTION
TQFN-EP
SSOP
7
10
DIN/A1
Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN
SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I2C device
address programming input and connects to DIN/A1 DGND or VL.
8
11
IRQ
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is
pending.
9
12
RST
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
In hardware reset mode, the oscillator and the internal PLL are shut down; there is no
clock activity.
10
13
VL
Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, and I2C/SPI. Bypass VL
with a 0.1FF ceramic capacitor to DGND. VL must be powered in all modes.
11
14
DGND
Digital Ground
12
15
GPIO0
General-Purpose Input/Output 0. GPIO0 is user programmable as an input or output
(push-pull or open drain). GPIO0 has a weak pulldown resistor to ground.
13
16
GPIO1
General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output
(push-pull or open drain). GPIO1 has a weak pulldown resistor to ground.
14
17
GPIO2
General-Purpose Input/Output 2. GPIO2 is user programmable as an input or output
(push-pull or open drain). GPIO2 has a weak pulldown resistor to ground.
15
18
GPIO3
General-Purpose Input/Output 3. GPIO3 is user programmable as an input or output
(push-pull or open drain). GPIO3 has a weak pulldown resistor to ground.
16
19
CTS
Active-Low Clear-to-Send Input. CTS is a flow-control input.
17
20
RTS/CLKOUT
Active-Low Request-to-Send Output. RTS/CLKOUT can be set high or low by pro-
gramming bit 7 (RTS) of the LCR register.
18
21
RX
Receive Input. Serial UART data input. RX has an internal weak pullup resistor to VEXT.
19
22
TX
Transmit Output. Serial UART data output.
20
23
VEXT
Transceiver Interface Level Supply. VEXT powers the internal logic-level translators for
RX, TX, RTS, CTS, and GPIO_. Bypass VEXT with a 0.1FF ceramic capacitor to
DGND.
21
24
XOUT
Crystal Output. When using an external crystal, connect one end of the crystal to
XOUT and the other to XIN. When using an external clock source, leave XOUT
unconnected.
22
1
XIN
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to
XIN and the other one to XOUT. When using an external clock source, drive XIN with
the external clock.
23
2
AGND
Analog Ground
24
3
VA
Analog Supply. VA powers the PLL and internal LDO. Bypass VA with a 0.1FF ceram-
ic capacitor to AGND.
EP
Exposed Paddle. Connect EP to AGND. EP is not intended as an electrical connec-
tion point. Only for TQFN-EP package.
Maxim Integrated
13
MAX3107
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