Dual I2S Stereo Audio Codec 10 ____________" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MAX9880AETM+T
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 2/70闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC CODEC AUDIO STEREO 48TQFN
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯欐簴鍖呰锛� 2,500
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鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� I²C锛孖²S锛屼覆琛�锛孲PI?
ADC / DAC 鏁�(sh霉)閲忥細 2 / 2
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鍕曟厠(t脿i)鑼冨湇锛屾婧� ADC / DAC (db)锛� 82 / 96
闆诲 - 闆绘簮锛屾ā鎿細 1.65 V ~ 1.95 V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 1.65 V ~ 1.95 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-WFQFN 瑁搁湶鐒婄洡
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鍖呰锛� 甯跺嵎 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
10
______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL =
鈭�, headphone load (RL) connected between _OUTP and _OUTN, dif-
ferential modes, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,
AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25掳C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
fMCLK
For any LRCLK sample rate
10
60
MHz
Prescaler = /1 mode
40
60
MCLK Input Duty Cycle
/2 or /4 modes
30
70
%
Maximum MCLK Input
Jitter
Maximum allowable RMS for performance limits
100
ps
DHF = 0
8
48
LRCLK Sample Rate
(Note 10)
DHF = 1
48
96
kHz
FREQ1 mode = 0x8 to 0xF
0
PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x
0
LRCLK Average
Frequency Error (Master
and Slave Modes)
(Note 11)
FREQ1 mode = Any clock other than above
-0.025
+0.025
%
Rapid lock mode
2
7
LRCLK PLL Lock Time
Any allowable LRCLK and
PCLK rate, slave mode
Nonrapid lock mode
12
25
ms
LRCLK Acceptable
Jitter for Maintaining
PLL Lock
Allowable LRCLK period change from nominal for
slave PLL mode at any allowable LRCLK and PCLK
rates
卤100
ns
Soft-Start/Stop Time
10
ms
CRYSTAL OSCILLATOR
Frequency
Fundamental mode only
12.288
MHz
Maximum Crystal ESR
100
Input Leakage Current
IIH, IIL
X1, TA = +25掳C
-1
+1
A
Input Capacitance
CX1, CX2
4
pF
Maximum Load
Capacitor
CL1, CL2
45
pF
DIGITAL INPUT (MCLK)
Input High Voltage
VIH
1.2
V
Input Low Voltage
VIL
0.6
V
Input Leakage Current
IIH, IIL
TA = +25掳C
-1
+1
A
Input Capacitance
10
pF
DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1)
Input High Voltage
VIH
0.7
x VDVDDS1
V
Input Low Voltage
VIL
0.3
x VDVDDS1
V
Input Hysteresis
200
mV
Input Leakage Current
IIH, IIL
TA = +25掳C
-1
+1
A
Input Capacitance
10
pF
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鍙冩暩(sh霉)鎻忚堪
MAX9880AEVKIT# 鍔熻兘鎻忚堪:闊抽牷 IC 闁嬬櫦(f膩)宸ュ叿 MAX9880A Eval Kit RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Evaluation Kits 椤炲瀷:Audio Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:TAS5614L 宸ヤ綔闆绘簮闆诲:12 V to 38 V
MAX9880AEVKIT+ 鍔熻兘鎻忚堪:闊抽牷 IC 闁嬬櫦(f膩)宸ュ叿 MAX9880A Eval Kit RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Evaluation Kits 椤炲瀷:Audio Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:TAS5614L 宸ヤ綔闆绘簮闆诲:12 V to 38 V
MAX9880AEWM+T 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC Stereo Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
MAX9880ETM+ 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:AUDIO CODEC - Rail/Tube
MAX9880EVKIT+ 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:STEREO AUDIO CODEC - Boxed Product (Development Kits)
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