Dual I2S Stereo Audio Codec _______________" />
參數(shù)資料
型號(hào)： MAX9880AETM+T
廠商： Maxim Integrated Products
文件頁數(shù)： 25/70頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO STEREO 48TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，I²S，串行，SPI?
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 82 / 96
電壓 - 電源，模擬： 1.65 V ~ 1.95 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（6x6）
包裝： 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
31
BITS
FUNCTION
PSCLK
MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz. PCLK = MCLK.
10 = Select if MCLK is between 20MHz and 40MHz. PCLK = MCLK/2.
11 = Select if MCLK is greater than 40MHz. PCLK = MCLK/4.
Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or
16kHz sample rates.
FREQ1[3:0]
PCLK (MHz)
LRCLK (kHz)
PCLK/LRCLK
0x00
Normal or PLL mode
0x1–0x7
Reserved
0x8
0x9
12
8
16
1500
750
0xA
0xB
13
8
16
1625
812.5
0xC
0xD
16
8
16
2000
1000
0xE
0xF
19.2
8
16
2400
1200
FREQ1
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK
ratio cannot be guaranteed, use PLL mode instead.
PLL1/PLL2
PLL Mode Enable
0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode,
the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects
an LRCLK as specified by the divide ratio.
1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal.
RLK1/RLK2
Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before
enabling the interface.
NI1/NI2
Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for
common NI values.
For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2):
NI = (65,536 x 96 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
fPCLK = Prescaled internal MCLK frequency (PCLK)
For LRCLK > 50kHz operation (DHF = 1 for DAI2):
NI = (65,536 x 48 x fLRCLK)/fPCLK
fLRCLK = LRCLK frequency
fPCLK = Prescaled internal MCLK frequency (PCLK)
Table 5. System and Audio Clock Registers (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9880AEVKIT# 功能描述:音頻 IC 開發(fā)工具 MAX9880A Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
MAX9880AEVKIT+ 功能描述:音頻 IC 開發(fā)工具 MAX9880A Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
MAX9880AEWM+T 功能描述:接口—CODEC Stereo Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9880ETM+ 制造商:Maxim Integrated Products 功能描述:AUDIO CODEC - Rail/Tube
MAX9880EVKIT+ 制造商:Maxim Integrated Products 功能描述:STEREO AUDIO CODEC - Boxed Product (Development Kits)
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