Dual I2S Stereo Audio Codec _______________" />
參數(shù)資料
型號(hào)： MAX9880AETM+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 29/70頁(yè)
文件大小： 0K
描述： IC CODEC AUDIO STEREO 48TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： I²C，I²S，串行，SPI?
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 82 / 96
電壓 - 電源，模擬： 1.65 V ~ 1.95 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-TQFN-EP（6x6）
包裝： 帶卷 (TR)
MAX9880A
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
______________________________________________________________________________________
35
BITS
FUNCTION
BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL =
010, unless sharing the bus with multiple devices.
BSEL
DESCRIPTION
000
Off (BCLK output held low)
001
64x LRCLK (192x internal clock divided by 3)
010
48x LRCLK (192x internal clock divided by 4)
011
128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.)
100
PCLK/2
101
PCLK/4
110
PCLK/8
BSEL1/2
111
PCLK/16
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when
operating in time-division multiplex mode.
SLOT
DESCRIPTION
00
Time slot 1
01
Time slot 2
10
Time slot 3
SLOTL1/2
SLOTR1/2
11
Time slot 4
Slot Data Delay (SLOTDLY1/SLOTDLY2)
In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following
information.
In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect.
SLOTDLY1/2[3:0]
DESCRIPTION
0xxx
Data for slot 4 begins immediately.
1xxx
Data for slot 4 delayed 1 BCLK cycle.
x0xx
Data for slot 3 begins immediately.
x1xx
Data for slot 3 delayed 1 BCLK cycle.
xx0x
Data for slot 2 begins immediately.
xx1x
Data for slot 2 delayed 1 BCLK cycle.
xxx0
Data for slot 1 begins immediately.
SLOTDLY1/2
xxx1
Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DHF
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path)
1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
Table 7. Digital Audio Interface Registers (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9880AEVKIT# 功能描述:音頻 IC 開(kāi)發(fā)工具 MAX9880A Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
MAX9880AEVKIT+ 功能描述:音頻 IC 開(kāi)發(fā)工具 MAX9880A Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
MAX9880AEWM+T 功能描述:接口—CODEC Stereo Audio CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9880ETM+ 制造商:Maxim Integrated Products 功能描述:AUDIO CODEC - Rail/Tube
MAX9880EVKIT+ 制造商:Maxim Integrated Products 功能描述:STEREO AUDIO CODEC - Boxed Product (Development Kits)
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