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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 17/70頁 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
28
MB86860 SPARClite
5. MB86860 BIU
The MB86860 Bus Unit (BIU) functions as an interface with the SS200 Core and external chip circuits. It operates at
frequency multiples (X2, X3, X4) of the external input clock, with a maximum of 100MHz. It consists of 3 modules: a Data
Buffer, an SDRAM Interface and a SPARClite Interface.
5.1. Data Buffer (DBU)
5.1.1. Instruction Buffer (IB)
Has valid-bits indicating that a 64-bit 4-column buffer, buffer data address-tag and data are valid. There are 4 valid-bits.
Reads 4 double-word data using burst transfers in addresses in sequence from requested addresses when there is a
miss in instruction buffer tags. Also outputs appropriate address double word data to IMB buses.
Outputs data corresponding to the appropriate addresses to IMB buses when there is a tag hit.
Instruction fetches from non-cache areas bypass buffers. Invalidates when there is a tag hit. Invalidates valid bits
when a MEXC signal is asserted.
Cache target areas are ASI=8 and ASI=9. Double word loads for these areas are regarded as instruction fetches.
Invalidates if there is a hit to an Atomic-load/Store instruction for ASI=8 and ASI=9 (handles as non-cache).
When FLUSH instructions are executed the IB is also flushed.
5.1.2. Read Buffer (RB)
Has two 64-bit 4-column buffers. Each buffer has a valid-bit which indicates that buffer data address tags and data are
valid. Has 1 tag and 1 valid-bit for double-words.
When buffer replacement is required, replacement is by means of an LRU algorithm.
Outputs data corresponding to the appropriate address to an IMB bus when an address in a load instruction hits a tag.
Reads 4 double-word data from external memory by addresses in sequence from the requested address and outputs data
corresponding to the appropriate addresses to IMB buses when an address in a load instruction misses all RB tags.
Bypasses buffers during execution of load instructions from non-cache areas. Invalidates when a tag is hit.
Handles Atomic-load/Store instructions as non-cache in all areas.
5.1.3. Write Buffer (WB
)
Outputs Store data via FIFO. BIU-BUS output is single transfers. FIFO is 64-bit X (16 columns-6 columns change
possible).
Overwrites to valid locations when, in case of bytes, half words and words, Store instructions are the same address as
the immediately preceding data (a FIFO input column tag is hit). (when Merge & Collapse is enabled).
Controls WB data with valid bits in byte units and reflects to the Byte Enable pin upon output.
Handles Atomic-load/Store instructions as non-cache in all areas.
5.1.4. Buffering Policy
The IB and RB are accessed in the order of instruction execution.
When Store Data hits in the first column of a WB, that data is rewritten. (when Merge and Collapse is enabled).
When Atomic-load/Store instructions are executed, WB contents is first written to memory, and the data is then read
from memory to the RB. If there is a hit in the RB, it is invalidated. Stores are handled as non-cache. After that, Stores
are then executed. Data is then handled as non-cache.
The order of data access between Read Buffers (RB) and Write Buffers (WB) is as shown below.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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