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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 36/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
47
MB86860 SPARClite
5.4. SPARClite Interface (SPB)
5.4.1. Functions as the basic interface connecting the SS200 to the SPARClite bus and has dedicated 32-bit address
bus and 64-bit data bus pins. Supports Burst Mode and Non-burst Transfer Mode. The SPARClite bus
interface operates at input clock frequency.
5.4.1.1. Overview of SPARClite Interface Operations
operatio
n
bus
cache/
data type
case
access times(burst/non-burst)
master
non-
SPARClite bus width
cache
64bit
32bit
16bit
8bit
region
read
data
cache
byte
BMREQ#
BMACK#
4 (burst)
8 (burst)
16 (burst)
32 (burst)
buffer
half word
assert
reply
word
BMACK#
4 (non-burst)
8 (non-burst)
16 (non-burst)
32 (non-burst)
double
not reply
word
non-
byte
BMREQ#
1 (non-burst)
cache
half word
not assert
1 (non-burst)
2 (non-burst)
word
1 (non-burst)
2 (non-burst)
4 (non-burst)
double
1 (non-burst)
2 (non-burst)
4 (non-burst)
8 (non-burst)
word
dmac
non-
cache
double
word
BMREQ#
assert
BMACK#
reply
4 (burst)
8 (burst)
16 (burst)
32 (burst)
BMACK#
not reply
4 (non-burst)
8 (non-burst)
16 (non-burst)
32 (non-burst)
write
data
buffer
cache
double
word+BE#
*1
BMREQ#
not assert
1 (non-burst)
2 (non-burst)
4 (non-burst)
8 (non-burst)
non-
byte
BMREQ#
1 (non-burst)
cache
half word
not assert
1 (non-burst)
2 (non-burst)
word
1 (non-burst)
2 (non-burst)
4 (non-burst)
double
word
1 (non-burst)
2 (non-burst)
4 (non-burst)
8 (non-burst)
dmac
non-
double
BMREQ#
BMACK#
4 (burst)
8 (burst)
16 (burst)
32 (burst)
cache
word
assert
reply
BMACK#
not reply
4 (non-burst)
8 (non-burst)
16 (non-burst)
32 (non-burst)
*1 Data merge and collapse happens. Therefore the data type cannot be decided
5.4.1.2. Burst Mode/Non-burst Mode
Read operations by Cache area reads and DMAC are basically processed as burst transfers. Thus, if BMREQ# is
asserted at the same time as AS# and BMACK# is returned in READY# timing for the initial access, a burst
transfer corresponding to the bus width is performed in Burst Mode. If BMACK# is not returned, a number of
non-burst transfers which corresponds to the bus width is performed.
In Burst Mode AS# is only asserted once, but the address changes sequentially every time READY# is returned,
and the address pin indicates the access destination address.
(1) Write operations to cache areas, (2) Atomic Load/Store operations and (3) Reads other than ASI=8,9,a,b are
handled as non-burst, and BMREQ# is therefore not asserted.
Since caches perform data valid/invalid control in double word units, the data read unit from cache areas is double
words regardless of the data type requested by the CPU. In a 64-bit bus, burst length is 4. BMREQ# is then
output, and if BMACK# is returned together with READY#, burst mode materializes, and burst transfers of the
lengths shown in the above table are performed. If BMACK# is not returned, burst transfers do not take place,
and the required number of single transfers as shown in the above table is performed. Burst length is 8 in 32-bit
bus, 16 in 16-bit bus and 32 in 8-bit bus. When burst transfers do not take place, the required number of single
transfers is performed as shown in the above table.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
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