參數(shù)資料
型號(hào): MB86860
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝: PLASTIC, BGA-352
文件頁(yè)數(shù): 20/70頁(yè)
文件大?。?/td> 1395K
代理商: MB86860
Specifications subject to changes without prior notice
31
MB86860 SPARClite
Table 5-3 Access Order between RB and WB (continued)
Access Type
hit judgment
Operation
Burst
Access
Cache Area
ASI==8, 9
IB: hit
First writes the WB to external memory, then reads data
from
OFF
(Data Access)
external memory or I/O and sends it to the CPU Core.
Continu-
IB: miss
ously stores data to external memory or I/O.
ASI==a, b
RB: hit
First writes the WB to external memory, then reads data
from
OFF
external memory or I/O and sends it to the CPU Core.
Continu-
RB: miss
ously stores data to external memory or I/O. Invalidates the
RB
if there is a hit to the RB.
ASI !=
DON’T
First writes the WB to external memory, then reads data
from
OFF
8,9,a, b
CARE
external memory or I/O and sends it to the CPU Core.
Continu-
ously stores data to external memory or I/O.
5.2. Data Buffer Tag Format
The following shows instruction buffer, read bufer and write buffer format.
INSTRUCTION BUFFER TAG
S
V
ADDRESS(27 bits)
READ BUFFER TAG
S
V
ADDRESS(27 bits)
X2
WRITE BUFFER TAG
ASI
V
ADDRESS(29 bits)
X6
S: Supervisor bit
Figure 5-1
V: Valid bit
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