- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69018 > MB86860 (FUJITSU LTD) 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 PDF資料下載
參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 47/70頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
Specifications subject to changes without prior notice
58
MB86860 SPARClite
2.
Activation by Internal Hardware Breaks
These break points are handled as synchronous traps. The following 2 conditions obtain for activating these traps:
A. The PC address matches IADR1/2, the PSR user/supervisor bits match the US1/2 bits (DSR Register) which
correspond to IADR, and the EIA1/2 bits of the DSR Register which correspond to these are set. Accordingly,
the EIA bit of the DCR Register, the IADR Register and the US bits must be set beforehand in order to activate
these break points. Instruction address breaks are before-type break points. Thus debug traps occur before
instructions with matching addresses are executed.
B. When the SSE bit of the DCR Register is set to “1”, the CPU is in Single Step Mode, and debug traps occur
following execution of each instruction without regard to PC or IADR values (there are several exceptions such
as RETT, WRPSR etc.). To activate this mode, the SSE bit of the DCR Register must be set.
3.
Software Breaks
The TA255 instruction (Trap always with tt=255) is a software debug trap instruction. This instruction activates
debug traps when the EN_BRK_ bit of the DSR Register is “0”.
6.2.3. Debug Trap Features
Debug trap priority is 2. It takes the highest priority when a reset is deleted.
All debug traps are trap type tt=225, and the trap address is 0x00000FF0. Trap base addresses (TBA) are ignored.
When the TDBP bit of the DCR Register is “1”, debug traps occur even during traps (ET=0).
When the TDBP bit of the DCR Register is “0”, ET=0 and hardware breaks and external breaks are ignored. Software
breaks (TA255) are activated even when ET=0.
Debug traps are activated only in Supervisor Mode.
Debug traps cannot be nested. Debug traps cannot again be activated during a debug trap. When the BG bit of the
DCR Register is “1”, break conditions other than TA255 are ignored, and traps are not activated. Software breaks
(TA255) during debug traps are abnormal, and the results are unpredictable. Try not to use TA255 instructions in debug
trap routines.
When debug trap routines are entered, condition codes (PSR CC fields) are not automatically saved by the hardware.
When the possibility exists that a debug trap routine may rewrite these, they must be saved and restored by the
softeware.
6.2.4. Debug Trap Operations
In addition to ordinary trap operations, the following operations are activated in debug traps:
ET –> pET
. . . ET bit saved to pET
PS –> pPS
. . . PS bit returned to pPS
1 –> DCR.BG . . . DCR Register bit is “1”
255 –> TBR.tt . . . (TBR tt field set to 255 only in software debug traps. tt fields are not rewritten by
software breaks and external breaks.
When there is again a return from a debug trap (JMPL+RETT is executed when DCR.BG is “1”), the next operation is
performed.
0 –> DCR.BG . . . DCR Register BG bit is “0”
pPS –> PS
. . . pPS bit returned to PS
pET –> ET
. . . pET bit returned to ET
pPS and pET are new bits for debug traps. They are assigned to bits 9 and 8 of the DSR Register.
6.2.5. BRKGO Output Pin
The MB86860 has a BRKGO output pin. This always reflects the DCR Register BG bit. When this bit is “1”, it indicates
that instruction fetches and data access are for debug trap routines. This pin can be used for debug trap routines in
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
| MB86934-60ZF | 32-BIT, 60 MHz, RISC PROCESSOR, CQFP256 |
| MB86936-25/50-PFV-G | 32-BIT, 25 MHz, RISC PROCESSOR, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
| MB86941 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86941PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
| MB86942PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Peripheral LSI for SPARClite |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。