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參數(shù)資料
| 型號： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁數(shù)： | 55/70頁 |
| 文件大小： | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
66
MB86860 SPARClite
11. MB86860 Signals
Table 11-1 SPARClite Bus Signals (1/3)
Pin Names
Pin Status
Explanation
(Attribute)
Sleep
Mode
Bus
Grant
RESET#
(input)
--------
System Reset. Asserting RESET# for at least 10 CLKIN cycles after the clock
has stabilized, causes the MB8686X to be initialized.
CLKIN
(input)
--------
Clock Input. This clock determine execution rate of SPARClite bus and timing of
MB8686X processor.
CLKSEL0
CLKSEL1
(input)
--------
Clock multiply mode select. These pins determine the clock multiply mode.
Internal operating frequency is determined by CLKIN and combination of
CLKSEL1 and CLKSEL0.
(CLKSEL1, CLKSEL0) == (0,0): Reserved,
(0,1): X2 mode,
(1,0): X3 mode,
(1,1): X4 mode.
AS#
(output)
O(Z)
Address Strobe . In the beginning of bus cycle, one clock period “L” is output.
Basically, a bus cycle starts with an assertion of AS# and terminated by an
assertion of READY# or RDYOUT#.
ASI<3:0>
(output)
O(Z)
ASI output . During a bus cycle, ASI<3:0> are valid similar to address signal.
ADR<31:2>
(output)
O(Z)
Address output. ADR<31:2> are signal for identifying instruction addresses or
data addresses. This signal are valid during bus cycle periods. Output values
during Idle cycles are not guaranteed.
During burst transfers, address signal
switch (incremented) at assertion of READY#.
Note: In case of 860 series, address are updated by wrap-round while in 830 series
address are updated by toggle mode. In 16-bit and 8-bit bus widths, ADR<1:0>
information are output on BE4# and BE5# pins.
D<63:0>
(input/output)
I(Z)
Data Bus. It is a bi-directional data bus used for instruction fetches, data loads
and data stores. Double word data types must be aligned in addresses which are
multiples of 8, word data types in addresses which are multiples of 4 and half word
data types in addresses which are multiples of 2 respectively. D<7:0> are used in
8-bit bus mode, D<15:0> in 16-bit bus mode and D<31:0> in 32-bit bus mode. Pull
up resistance should be attached to unused data bus pins if entire address space
are assigned to 8 or 16 or 32bit bus width.
DP0~DP7
(input/output)
I (Z)
I(Z)
Data Parity. These signals are parity input during reads and parity output
during writes. DP0 correspond to parity of D<63:56>. DP1 to DP7 correspond to
D<55:48> to D<7:0> respectively. In 32-bit bus mode, DP4~DP7 are used, in 16-bit
bus mode DP6 and DP7, and in 8-bit bus mode DP7 is used. Pull up resistance
should be attached if unused DP signals exist.
RD#
(output)
O(Z)
Read Signal. When the current bus cycle is a READ cycle, “L” is output, and
in WRITE cycle or IDLE cycle periods “H” is output. Output level is maintained
from the beginning to the end of a bus cycle. This signal has been added to the
SPARClite -830 Series. In order to maintain design compatibility with the 830
Series, use only RDWR# signals when doing your designing.
RDWR#
(output)
O(Z)
Read/write signal. When the current bus cycle is a WRITE cycle “L” is
output, and in READ cycle or IDLE cycle periods “H” is output. Output level is
maintained from the beginning to the end of a bus cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB86930-30ZF-G-BND | 制造商:FUJITSU 功能描述: |
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