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參數(shù)資料
| 型號(hào)： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 48/70頁(yè) |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
59
MB86860 SPARClite
ROM chip select. Instructions and data indicated by BRKGO are not cached.
6.2.6. Register Files
Handling of debug trap register files is the same as for ordinary traps, and CWP is decremented. Handling of debug trap
routine register files is left entirely to the software.
6.2.7. PC Trace Features
PC trace information is stored in 16-column cyclic registers mapped in the one ASI=0x01 memory space. In Debug Mode,
as instructions are fetched their addresses are stored in this register until a break is activated. If the trace register is full
before a break is activated, the new address is written over the oldest register (cyclic operation).
Break trap routines can read those registers in which ASI=0x01 addresses 0x0000FF40~0x0000FF7C are mapped. The
TBPTR Field of the DSR Register holds the register addresses which are the PC addresses stored last. The newest
register addresses can be obtained by shifting the TBPTR field to bits 5~2 and doing 0x0FF40 and OR. For example, if
TBPTR is 5 and it is shifted, it becomes 0x14, and if 0x0FF40 and OR is done, 0xFF54 is obtained. The nearest traces are
stored in this register, and under it Reg4, Reg3, . . .Reg0, Reg15, Reg 14, . . . becomes effective.
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