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| 型號： | MB86960APF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 376K |
| 代理商： | MB86960APF-G |
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MB86960
45
t1
t3
t2
t5
t4
t6
t9
t8
t7
t10
SA0-3
CS
RD
RDY
SD15-0
(from NICE)
t11
Figure 16. Read Cycle
TRISTATE
Table 21. Read Cycle
Symbol
Parameter Description
Min.
Max.
Units
t1
CS low to RD low; SA3–0 valid to RD low
3
ns
t2
RD high to CS high; RD high to SA3–0 invalid
3
ns
t3
RD low pulse width
30
ns
t4
RD low to RDY low
0
26
ns
t5
RD low to RDY TRISTATE [1]
175
ns
t6
RD low to RDY low [2]
0
175
ns
t7
RD high to RDY TRISTATE
28
ns
t8
RD low to SD15–0 valid (except Buffer Memory Port)
44
ns
t9
RDY TRISTATE to SD15–0 valid (buffer port)
8
ns
t10
RDY low to SD15–0 valid
10
ns
t11
RD high to SD15–0 invalid (data hold)
15
ns
1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the read cycle begins. For port access only, 175 ns
maximum may occur if system makes contiguous system read cycles at less than 100 ns intervals, and both the transmitter and receiver
are active in “l(fā)oopback” reception. 2.15
s max for bus read error.
2. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system read cycles at
less than 100 ns intervals, and both the transmitter and receiver are active in “l(fā)oopback” reception. 2.15
s max for bus read error.
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