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| 型號： | MB86960APF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 41/66頁 |
| 文件大小： | 376K |
| 代理商： | MB86960APF-G |
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MB86960
46
t1
t3
t2
t5
t4
t6
t9
t8
t7
SA0-3
CS
RD
RDY
SD15-0
(to NICE)
Figure 17. Write Cycle
TRISTATE
Table 22. Write Cycle
Symbol
Parameter Description
Min.
Max.
Units
t1
CS low to WE low; SA3–0 valid to WE low
3
ns
t2
WE high to CS high; WE high to SA3–0 invalid
3
ns
t3
WE low pulse width
36
ns
t4
WE low to RDY low
0
26
ns
t5
WE low to RDY TRISTATE [1]
175
ns
t6
WE low to RDY low [2]
0
175
ns
t7
WE high to RDY TRISTATE
28
ns
t8
SD15–0 valid to WE high (data setup)
5
ns
t9
WE high to SD15–0 invalid (data hold)
6
ns
1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the write cycle begins. For port access only, 175 ns
maximum may occur if system makes contiguous system write cycles at less than 100 ns intervals, and both the transmitter and receiver
are active in “l(fā)oopback” reception.
2. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system write cycles at
less than 100 ns intervals, and both the transmitter and receiver are active in “l(fā)oopback” reception.
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