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參數資料
| 型號： | MB86960APF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 56/66頁 |
| 文件大小： | 376K |
| 代理商： | MB86960APF-G |
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MB86960
6
PIN DESCRIPTIONS
Buffer Memory Interface Pins
SYMBOL
TYPE
DESCRIPTION
BCS0
O
BUFFER CHIP SELECT:Active low. BCS1 and BSC0 are the chip select lines, most significant
BCS0
BSC1
O
BUFFER CHIP SELECT:Active low. BCS1 and BSC0 are the chi select lines, most significant
byte and least significant byte respectively, of the dedicated buffer SRAM.
BOE
O
BUFFER OUTPUT ENABLE: This active low signal is the output enable for the Buffer SRAM, and
is asserted by NICE during buffer memory read cycles.
BWE
O
BUFFER WRITE ENABLE: Active low. Used as a write strobe to the buffer SRAM memory during
write operations.
BD<15:0>
B
BUFFER DATA: Data lines between the SRAM buffer memory and NICE. This SRAM data bus is
configurable for an 8-bit or 16-bit data size by BUFFER BYTE/BUFFER WORD, BB/BW, in
DLCR6<4>. The transfer byte order within a word, most significant or least-significant byte first, is
determined by DATA_ORDER, DLCR7<1>.
BA<15:0>
O
BUFFER ADDRESS: These lines address up to 64 kilobytes of SRAM buffer memory.
Network Interface Pins
SYMBOL
TYPE
DESCRIPTION
TXDATA+
O
TRANSMIT INTERFACE PAIR: These are the differential outputs to the transceiver for transmitting.
TXDATA+
TXDATA–
O
TRANSMIT INTERFACE PAIR: These are the differential out uts to the transceiver for transmitting.
RXDATA+
I
RECEIVED DATA: These are the Manchester differential inputs from the transceiver to the receiver.
RXDATA+
RXDATA–
I
RECEIVED DATA: These are the Manchester differential in uts from the transceiver to the receiver.
COL+
COL–
I
COLLISION: These differential inputs are driven with a 10 MHz signal when the transceiver detects a
collision on the media.
AC/DC
I
AC/DC COUPLING SELECT: AC/DC = 1 selects AC coupling; 0 selects DC coupling for the
TXDATA
± outputs. When AC coupling is selected, both TXDATA+ and TXDATA– are driven to the
same output voltage level during the transmit idle period to prevent saturation of the isolation
transformer. With DC coupling, these outputs remain at a 1 level during idle periods.
System Clock Pins
SYMBOL
TYPE
DESCRIPTION
X1
I
CRYSTAL INPUT: Connection for one side of the 20 MHz crystal, or input for an external 20 MHz
clock source.
X2
O
CRYSTAL OUTPUT: Connection for the other side of the 20 MHz crystal. Leave unconnected if an
external clock is used.
CKOUT
O
CLOCK OUTPUT: 20 MHz free-running clock output provided by the crystal
oscillator circuit.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APD-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86961APF-G | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
| MB86965 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
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