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參數(shù)資料
| 型號： | MBM29DL64DF70PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| 中文描述： | 4M X 16 FLASH 3V PROM, 70 ns, PBGA48 |
| 封裝： | PLASTIC, FBGA-48 |
| 文件頁數(shù)： | 35/68頁 |
| 文件大?。?/td> | 854K |
| 代理商： | MBM29DL64DF70PBT |
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MBM29DL64DF
-70
35
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend Mode or sector erase time-out. See Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the busy bank results in DQ
6
toggling between one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ
6
stops toggling and valid data is read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In Program Operation, if the sector being written to is protected, the toggle bit toggles for about 1
μ
s and then
stops toggling with data unchanged. In erase operation, the device erases all selected sectors except for pro-
tected ones. If all selected sectors are protected, the chip toggles the toggle bit for about 400 μs and then drop
back into read mode, having data kept remained.
Either CE or OE toggling causes DQ
6
to toggle.
DQ
6
determines whether a sector erase is active or is erase-suspended. When a bank is actively erased (that
is, the Embedded Erase Algorithm is in progress) , DQ
6
toggles. When a bank enters the Erase Suspend mode,
DQ
6
stops toggling. Successive read cycles during erase-suspend-program cause DQ
6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” (in
I
TIMING DIAGRAM) in for
the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
indicates if the program or erase time exceeds the specified limits (internal pulse count) . Under these
conditions DQ
5
produces “1”. This is a failure condition indicating that the program or erase cycle was not
successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit
partially powers down device under these conditions (to approximately 2 mA) . The OE and WE pins control the
output disable functions as described in User Bus Operations.
The DQ
5
failure condition may also appear if the user tries to program a non-blank location without pre-erase.
In this case the device locks out and never completes the Embedded Algorithm operation. Hence the system
never reads valid data on DQ
7
bit and DQ
6
never stop toggling. Once the device exceeds timing limits, the DQ
5
bit indicates a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
DQ
3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ
3
remains low
until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates that a valid erase command is written, DQ
3
determines whether the
sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase cycle begins. If DQ
3
is
low (“0”) , the device accepts additional sector erase commands. To insure the command is accepted, the system
software checks the status of DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
is high
on the second status check, the command may not be accepted.
See Hardware Sequence Flags.
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PDF描述 |
|---|---|
| MBM29DL64DF70TN | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL800TA | 8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-70 | LED Lamp; Bulb Size:T-1 3/4; LED Color:Red; Luminous Intensity:2000ucd; Viewing Angle:16 ; Forward Current:20mA; Forward Voltage:1.9V; Operating Temperature Range:-25 C to +85 C; Color:Red; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| MBM29DL800BA-90 | LED Lamp; Bulb Size:T-1 3/4; LED Color:Yellow; Luminous Intensity:2500ucd; Viewing Angle:15 ; Forward Current:20mA; Forward Voltage:2.1V; Operating Temperature Range:-40 C to +85 C; Color:Yellow; Leaded Process Compatible:Yes RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL64DF70TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL800BA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-70PBT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 8M (1M x 8 / 512K x 16) BIT |
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