參數(shù)資料
型號(hào)： MBM29LV200T-10
廠商： Fujitsu Limited
英文描述： CMOS 2M (256K×8/128K ×16) Bit Flash Memory(2M (256K×8/128K ×16)位 單5V 電源電壓閃速存儲(chǔ)器)
中文描述： 200萬(wàn)的CMOS（256K × 8/128K × 16）位閃存（200萬(wàn)（256K × 8/128K × 16）位單5V的電源電壓閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 16/50頁(yè)
文件大?。?/td> 469K
代理商： MBM29LV200T-10
16
MBM29LV200T
-10/-12
/MBM29LV200B
-10/-12
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-
istics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H for
×
16 (XX02H for
×
8) returns the device code (MBM29LV200T = 3BH and
MBM29LV200B = BFH for
×
8 mode; MBM29LV200T = 223BH and MBM29LV200B = 22BFH for
×
16 mode).
(See Tables 4.1 and 4.2.)
All manufacturer and device codes will exhibit odd parity with DQ
7
defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02H for
×
16 (XX04H for
×
8).
Scanning the sector addresses (A
16
, A
15
, A
14
, A
13
, and A
12
) while (A
6
, A
1
, A
0
) = (0, 1, 0) will produce a logical “1”
at device output DQ
0
for a protected sector. The programming verification should be perform margin mode on
the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence the
system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may hang up the device according to the data polling algorithm
(Please refer to Figure 20.). Read from read/reset mode will show that the data is still “0”. Only erase operations
can convert “0”s to “1”s.
Figure 18 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
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參數(shù)描述
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