參數(shù)資料
型號: MC33780EG
廠商: Freescale Semiconductor
文件頁數(shù): 20/37頁
文件大?。?/td> 0K
描述: IC DBUS MASTER DUAL DIFF 16-SOIC
標(biāo)準(zhǔn)包裝: 47
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 23. State Diagram of Receive FIFO
REGISTER AND BIT DESCRIPTIONS
The 33780 has 22 registers, shown in Table 8. The lower
8 (00000 through 00111) are compatible with the 8 registers
in the 68HC55. The remaining registers (01000 through
10101) are needed for the additional modes of operation.
RX_IDLE
RX_NOT_EMPTY
RX_FULL
~EN or ABORT or RSTB ACTIVE/
R_PUSH_PTR = 0;
R_POP_PTR = 0;
R_FIFO_EMPTY = TRUE;
R_FIFO_POP & R_POP_PTR = R_PUSH_PTR-1/
R_POP_PTR = R_POP_PTR+1;
R_FIFO_EMPTY = TRUE;
R_FIFO_POP & R_POP_PTR != R_PUSH_PTR-1/
R_POP_PTR = R_POP_PTR+1;
R_FIFO_POP/
R_FIFO_POP = R_FIFO_POP+1;
R_FIFO_PUSH & R_PUSH_PTR = R_POP_PTR-1/
R_PUSH_PTR = R_PUSH_PTR+1;
R_FIFO_PUSH & R_PUSHPTR != R_POP_PTR-1/
R_PUSH_PTR = R_PUSH_PTR+1;
R_FIFO_PUSH/
R_PUSH_PTR = R_PUSH_PTR+1;
R_FIFO_EMPTY = FALSE;
OVERFLOW = FALSE;
STATE TRANSISTIONS OCCUR
ON NEGATIVE EDGES OF R_FIFO_PUSH
AND R_FIFO_POP
Table 8. Register List
Register
Address
Register Name
Register Definition
00000
D0H
DBUS 0 upper byte
00001
D0L
DBUS 0 lower byte
00010
D1H
DBUS 1 upper byte
00011
D1L
DBUS 1 lower byte
00100
D01STAT
DBUS 0 and 1 status
00101
D0CTRL
DBUS 0 control
00110
D1CTRL
DBUS 1 control
00111
DEN
DBUS enable bits
01000
D0POLY
DBUS 0 CRC polynomial
01001
D1POLY
DBUS 1CRC polynomial
01010
D0SEED
DBUS 0 CRC seed
01011
D1SEED
DBUS 1 CRC seed
01100
D0LENGTH
DBUS 0 short word and CRC lengths
01101
D1LENGTH
DBUS 1 short word and CRC lengths
01110
D0SSCTRL
DBUS 0 spread spectrum control
01111
D1SSCTRL
DBUS 1spread spectrum control
10000
D0OFFSETH
DBUS 0 spread spectrum offset high
10001
D0OFFSETL
DBUS 0 spread spectrum offset low
10010
D1OFFSETH
DBUS 1 spread spectrum offset high
10011
D1OFFSETL
DBUS 1 spread spectrum offset low
10100
D0SSUD
DBUS 0 spread spectrum up/down counter
10101
D1SSUD
DBUS 1 spread spectrum up/down counter
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