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| 型號： | MC33780EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/37頁 |
| 文件大小： | 0K |
| 描述： | IC DBUS MASTER DUAL DIFF 16-SOIC |
| 標準包裝： | 47 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33780
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33780 is intended to be used as a master device in a
distributed system. It contains both protocol generators and
physical interfaces to allow an MCU to communicate with
devices on the bus using only a simple SPI interface. Two
differential busses are provided.
Using a loop-back wire allows operation of the bus in the
presence of an open circuit. This is immediate and no
interruption is caused by the open circuit. The differential
outputs have reduced electromagnetic radiation and
susceptibility.
The equivalent bus capacitance consists of capacitors
connected between the two bus wires and capacitors
between the bus wires and ground. Because the voltage
change on either of the bus wires to ground is only 1/2 the
amount of change between the two bus wires, the
capacitance to ground only conducts half as much current as
it would if connected directly across the bus. The equivalent
bus capacitance of a capacitor to ground from the bus wires
is one half of the actual amount of the capacitor. The amount
of capacitance from either bus wire to ground should be kept
the same in order to achieve the lowest radiated EMI energy.
The 4.7 nF capacitors required between the bus wires and
ground result in an equivalent of 2.35 nF of capacitance
across the bus as seen by either bus wire.
Table 5 shows the voltages used for operation. Low side
(LS) is the bus wire that is the most negative and high side
(HS) is the bus wire that is the most positive. Figure 5 shows
the bus waveforms in normal operation.
FUNCTIONAL PIN DESCRIPTIONS
RESET (RST)
When pulled low, this will reset all internal registers to a
known state as indicated in the section entitled Register and Bit
CHIP SELECT (CS)
This input is used to select the SPI port when pulled to
ground. When high, the SPI signals are ignored. The SPI
transaction is signaled as completed when this signal returns
high.
INTERRUPT (INT)
This output will be asserted ow when an enabled interrupt
condition occurs. It contains an internal current pull-up
source so that it will remain high when not active. The output
is open-drain so that it can be ORed together with other open-
drain outputs so that this IC or any of the others can assert an
interrupt.
MASTER OUT/SLAVE IN (MOSI)
This is the SPI data input to the device. This data is
sampled on the positive (rising) edge of SCLK.
SERIAL CLOCK (SCLK)
This is the clock signal from the SPI master device. It
controls the clocking of data to the device and data read from
the device.
MASTER IN/SLAVE OUT (MISO)
This is the SPI data from the device to the SPI master (the
MCU). Data changes on the negative (falling) transition of the
SCLK.
CLOCK (CLK)
This is the main clock source for the internal logic. It must
be 4.0 MHz.
GROUND (GND)
Ground source for both logic and DBUS return.
POWER SOURCE (VCC)
Logic power source. Nominal value is +5.0 V. This should
be bypassed with a small capacitor to ground (0.01-0.1 F)
LOW-SIDE BUS (DnL)
There are two independent LOW-SIDE outputs, D0L and
D1L They comprise the low-side differential output signal of
Table 5. High-Side and Low-Side Typical Voltages (Voltage Relative to Ground)
Low Side
High Side
IDLE
HIGH
LOW
IDLE
HIGH
LOW
0
Vmid-2.25 (18)
Vmid-0.75 (18)
VSUP
Vmid+2.25 (18)
Vmid+0.75 (18)
Notes
18
Vmid = VSUP/2.
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