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| 型號： | MC33780EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 24/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DBUS MASTER DUAL DIFF 16-SOIC |
| 標準包裝： | 47 |
| 系列： | * |
| 類型： | * |
| 應用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
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Analog Integrated Circuit Device Data
30
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DnCTRL REGISTER
The read/write DnCTRL register sets up conditions to be
used on the DBUS. There are two of these registers, one for
each of the buses. The bit assignments are shown in
Figure 28. Dn Control Register Bit Assignment
Each output n has an associated DnCTRL register. This
register should be written to before data is sent over its bus.
A write to the register will abort any current activity on the bus.
Any bit changes will take place on the next DBUS transaction
following the conclusion of the SPI write to the register. Refer
to the Protocol Engine section for more detail.
DLY[B:A]–Interframe Delay for Channel n
These bits specify the minimum delay between transfer
frames on the bus as illustrated in Table 9. For example,
when DLY[B:A] is set to 00, there is a minimum of four bit
times of IDLE voltage level. The time is measured from the
end of a DBUS transaction (signaled by the start of the signal
high to IDLE voltage transition) to the start of a new DBUS
transaction (signaled by the start of the IDLE voltage to signal
high transition).
RIE–Receive Interrupt Enable Channel n
0 = Receive interrupt disabled. RFNE status does not
affect INT pin.
1 = Receive interrupt enabled. Whenever the RFNE
status flag is 1, the INT pin will be low to request an
interrupt.
TIE–Transmit Interrupt Enable Channel n
0 = Transmit interrupt disabled. TFE status does not
affect INT pin.
1 = Transmit interrupt enabled. Whenever the TFE
status flag is 1, the INT pin will be low to request an
interrupt.
MS–Message Size for Channel n
0 = Long Word.
1 = Short Word
The Long Word will contain 16 bits of data and 0 to 8 bits
of CRC. The Short Word can be made to have between 8 and
15 bits of data and 0 to 8 bits of CRC. Long words are
generally used for configuration and setup messages. Short
words are generally used for DBUS data transactions.
DIV[1:0]–Clock Divider
The DIV bits set a pre-scaler for the bit clock to allow the
bit rate to be reduced by selectable integer values. The
divider values are shown in Table 10. The clock divider is
used during fixed frequency operation and is ignored when in
the spread-spectrum mode.
DEN Register
This read/write register is used to enable or disable each
of the busses. It also allows the state of the thermal
shutdowns to be read. The bit assignments are shown in
Figure 29. If a thermal shutdown occurs, the output of the bus
driver will be tri-stated and the receive current detector
disabled. This will result in an all 0 response, which will cause
a CRC error.
Figure 29. DEN Register Bits
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
DIV1
DIV0
DLYB
DLYA
RIE
TIE
0
MS
Reset
0
Table 9. DLY[B:A] Frame Spacing
DLY[B:A]
Minimum Delay Between Frames
(Bit Times)
00
4
01
5
10
6
11
8
Table 10. Clock Divider
DIV[1:0]
N
00
1
01
2
10
4
11
8
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
TS1
(Read-Only)
TS0
(Read-Only)
0
EN1
EN0
Reset
0
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