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| 型號： | MC33780EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 28/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DBUS MASTER DUAL DIFF 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
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Analog Integrated Circuit Device Data
34
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
PROTECTION AND DIAGNOSIS FEATURES
For handling fault conditions on the DBUS, the driver
includes overcurrent and thermal protection and an
overvoltage operating mode.
OVERCURRENT PROTECTION
Current limiters on the outputs prevent damage in the case
of shorts. Running in-current limit results in high power
dissipation of the IC. If the power dissipation becomes high
enough, the die temperature will rise above its maximum
rating and an overtemperature circuit on the IC will shut down
the DBUS Driver/Receiver block.
The Idle driver has current limits for protection of both this
device and slave devices connected on the DBUS. The DnH
driver has a high value current limit when it is sourcing current
to allow the driver to charge the slave power storage
capacitors, and a lower value current limit when sinking
current and slewing the load capacitance. Conversely, the
DnL driver has a high value current limit when it is sinking
current, and a lower value current limit when it is sourcing
current.
The overcurrent protection for the Signal driver
incorporates a gross current limit and an over current
shutdown. The current shutdown is set at a low value, such
that the Signal driver will shut down if the sourcing or sinking
current remains at a value larger than the response current.
The overcurrent shutdown is delayed by a filter to allow the
load capacitors to be slewed without causing a shutdown.
The purpose of the gross current limit is to protect the drivers
during the filter delay time. This current limit is set higher than
the peak current required to slew the load capacitance.
The signals from the sourcing and sinking current
detection circuits are connected to a logical OR. The
combined signal passes through a common filter before
setting the overcurrent latch. In overcurrent shutdown the
entire Signal driver will be shut down and the DBUS will be
high impedance until the end of Frame, when the DBUS
returns to the Idle state. In addition, the output of the OR gate
is logically OR’ed with the CRC error hit ERx which can be
read in register DO1STAT (see Figure 28).
The end of Frame will clear the overcurrent shutdown
state, allowing the Signal driver to retry in the next Frame.
THERMAL PROTECTION
Independent thermal protection is provided for each
DBUS. The thermal limit cell is located adjacent to the Idle
and Signal drivers for each channel, such that both drivers
are protected. When a thermal fault is detected, the driver is
disabled (Hi-Z) until it is re-enabled via the SPI. The thermal
protection incorporates hysteresis preventing the DBUS from
being re-enabled until the temperature has decreased.
Thermal fault information is reported via the DEN register.
See DEN Register section for a description of the fault
reporting and clearing of the EN bits.
LOAD DUMP OPERATION
During an overvoltage condition (e.g., when load dump is
applied at the VSUP pin), the DBUS voltage waveform is
modified to ensure that power dissipation is minimized,
DBUS timing is not violated, and internal components are
protected.
The midpoint of the signalling voltage is clamped at about
13 V such that, for VSUP greater than 26 V, the signalling
voltage levels do not increase. An overvoltage detection
circuit connected to DnH, having a threshold at about 26 V,
causes the slew rates and driver conditions to be modified.
For a Signal-to-Idle transition, this causes the DnH voltage to
rise rapidly to the Idle state and the DnL voltage is maintained
close to zero. For an Idle-to-Signal transition, the DnH
voltage will decrease rapidly until the overvoltage threshold is
reached, when normal operation resumes. During this rapid
fall of DnH, the DnL voltage is maintained close to zero by
forcing that driver on. See Figure 6.
RESET FUNCTION
A low level on RST forces the internal registers to a known
state. The receive and transmit FIFO pointers are reset and
the FIFOs are cleared. Because the DBUS channels are now
disabled (ENn = 0), the DBUS lines are tri-stated.
ABORT FUNCTION
An abort is generated whenever a control register
(DnCTRL, DnPOLY, DnSEED, DnLENGTH, or DnSSCTRL)
is addressed while writing, even if the data is unchanged. No
other register writes cause an abort. Reads of any register do
not cause an abort. The DEN register is not affected by an
abort. The abort occurs as soon as the address of the control
register is received on the SPI. Any DBUS transfer that was
in progress is stopped, and DBUS lines return to their Idle
states. The abort condition remains true throughout the SPI
write to the DBUS control registers. After the last bit of the
DBUS control register is written, the transmit and receive
FIFO pointers are reset and FIFO data is cleared. The
programmed inter-frame delay is then enforced (using the
new values of the delay control bits) to allow reservoir
capacitors in remote nodes to charge. In the case of DLY
changing, any partial inter-frame delay based on old control
settings is lost.
ENABLE (DISABLE) FUNCTION
When a DBUS channel is disabled, the 33780 device
forces its bus output to tri-state. The transmit and receive
FIFO pointers are reset and the FIFO locations are forced to
zero. Any DBUS transfer that was in progress is stopped.
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