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| 型號(hào)： | MC33780EG |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 26/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DBUS MASTER DUAL DIFF 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
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Analog Integrated Circuit Device Data
32
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SWLEN[3:0]–Short Word Length in Bits
These bits specify the bit length of the short word
command that will be sent onto the specified DBUS channel.
The reset value for these bits is 1000 (8 bits), which is the
default DSI value. Allowed SWLEN[3:0] values range from
8 bits to 15 bits. If an attempt is made to write a value that is
less than 8 bits, a 1 is automatically written to SWLEN3,
thereby making the register value greater than or equal to 8
bits.
Note If a SWLEN[3:0] value greater than 8 bits is chosen,
it is necessary to write a full 8 bits into both the DnL and DnH
registers with an SPI command, even though there will be
some MSBs of DnH that are not sent out on the DBUS.
Similarly, to read the data back onto the SPI, it is necessary
to read the full DnL and DnH registers, ignoring unused DnH
bits.
The SWLEN3 bit is not used, since words less than 8 bits
are not allowed. When reading the SWLEN3, bit 0 is always
return; however, the logic interprets the bit as if it were a 1.
CRCLEN[3:0]–CRC Length in Bits
These bits specify the bit length of CRCs that are sent out
with commands and read back in. The length is valid for both
short and long word commands. The reset value for these
bits is 0100 (4 bits), which is the default DSI value. Allowed
CRCLEN[3:0] values range from 0 bits (no CRC) to 8 bits. If
an attempt is made to write a value that is greater than 8 bits,
the value 8 (1000) is automatically written into this register.
The CRCLEN[3:0] value overrides the CRCPOLY and
CRCSEED bit values that are beyond what the CRCLEN[3:0]
specifies.
DnSSCTRL REGISTERS
These registers control the operation of the spread
spectrum circuits.
A write to the register will abort any current activity on the
bus. Any bit changes will take place on the next DBUS
transaction following the conclusion of the SPI write to this
register. The bit assignments are shown in Figure 33.
Figure 33. Dn Spread Spectrum Control Register Bit Assignments
SSEN–Spread Spectrum Enable for Channel n
This bit enables spread spectrum on the particular channel
that is specified. With deviation enabled, the DBUS bit
periods will be pseudo-randomly varied from one bit to the
next, while keeping the time between successive Frame
edges constant. The DBUS data rate will be controlled by a
programmable PLL loop, rather than the 4.0 MHz external
clock.
PLLOFF–Spread Spectrum PLL Disable for Channel n
This bit disables the PLL loop updating of the DBUS
frequency. The PLL adjusts the spread spectrum frequency
up and down by comparing it to a divided down version of the
external 4.0 MHz clock. If the internal spread spectrum clock
is stable, then it is useful to be able to turn off the PLL
updates, thus avoiding clock jitter. In order to change the
frequency of the PLL, PLLOFF must be reset. A write
operation to the frequency offset registers is not allowed
while PLLOFF is set.
PRBS[1:0]–Pseudo-Random Binary Sequence
Register Length for Channel n
These bits control the length of the Pseudo-Random
Binary Sequence register (PRBS). The PRBS is used to
randomize the DBUS spread spectrum frequencies, and
choosing different lengths will change the XOR tap position
on the PRBS. The following Table 11 describes the bit
encoding of this field.
SPI Data Bit
Bit 7
6
5
4
3
2
1
0
Read/Write
0
SSEN
PLLOFF
PRBS1
PRBS0
DEV1
DEV0
Reset
0
Table 11. PRBS Bit Encoding
PRBS[1:0]
PRBS Reg
Length
XOR Input A
XOR Input B
00
6
5
4
01
7
6
5
10
11
10
8
11
15
14
13
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