參數(shù)資料
型號(hào): MC33780EG
廠商: Freescale Semiconductor
文件頁數(shù): 35/37頁
文件大?。?/td> 0K
描述: IC DBUS MASTER DUAL DIFF 16-SOIC
標(biāo)準(zhǔn)包裝: 47
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33780
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V
≤ V
CC ≤ 5.25 V, 9.0 V ≤ VSUP ≤ 25 V, - 40°C ≤ T
A ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CLOCK
CLK Periods
Time High
Time Low
Period (System requirement) (8)
tCLKHI
tCLKLO
tCLKPER
75
245
250
255
ns
CLK Transition (System requirement) (8)
Time for Low-to-High Transition of the CLK Input Signal
Time for High-to-Low Transition of the CLK Input Signal
tCLKLH
tCLKHL
50
ns
Reset Low Time
tRSTLO
100
ns
SPI INTERFACE TIMING
SPI Clock Cycle Time
tCYC
200
ns
SPI Clock High Time
tHI
80
ns
SPI Clock Low Time
tLO
80
ns
SPI CS Lead Time (9)
tLEAD
100
ns
SPI CS Lag Time (9)
tLAG
100
ns
SPI SCLK Time Between Bytes (8)
tHI
80
ns
SPI CS Time Between Bursts (8)
tCSHI
80
ns
Data Setup Time
MOSI Valid Before SCLK Rising Edge (9)
tSU
25
ns
Data Hold Time
MOSI Valid After SCLK Rising Edge (9)
MISO Valid After SCLK Falling Edge (8)
tH
tHO
25
0
ns
Data Valid Time
SCLK Falling Edge to MISO Valid, C = 100 pF
tV
50
ns
Output Disable Time
CS
Rise to MISO Hi-Z
tDIS
100
ns
Rise Time (30% VCC to 70% VCC)
SCLK, MISO
tR
25
ns
Fall Time (70% VCC to 30% VCC)
SCLK, MISO
tF
25
ns
Notes
8
Not measured in production.
9
SPI signal timing from the production test equipment is programmed to ensure compliance.
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