System Integration Block (SIB)
MOTOROLA
MC68302 USER’S MANUAL
3-55
2. BG will be an input to the IDMA and SDMA from the external M68000 bus, rather than
being an output from the MC68302. When BG is sampled as low by the MC68302, it
waits for AS, BERR, HALT, and BGACK to be negated, and then asserts BGACK and
performs one or more bus cycles. See Section 6 for timing diagrams.
3. BCLR will be an input to the IDMA, but will remain an output from the SDMA.
4. The interrupt controller will output its interrupt request lines (IPL0, IPL1, IPL2) normally
sent to the M68000 core on pins IOUT0, IOUT1, and IOUT2, respectively. AVEC,
RMC, and CS0, which share pins with IOUT0, IOUT1, and IOUT2, respectively, are
not available in this mode.
DISCPU should remain continuously high during disable CPU mode operation. Although the
CS0 pin is not available as an output from the device in disable CPU mode, it may be en-
abled to provide DTACK generation. In disable CPU mode, BR0 is initially $C000.
Accesses by an external master to the MC68302 RAM and registers may be asynchronous
or synchronous to the MC68302 clock. (This feature is actually available regardless of dis-
able CPU mode). See the SAM and EMWS bits in the SCR for details.
In disable CPU mode, the interrupt controller may be programmed to generate or not gen-
erate interrupt vectors during interrupt acknowledge cycles. When multiple MC68302 devic-
es share a single M68000 bus, vector generation at level 4 should be prevented on all but
one MC68302. When using disable CPU mode to implement an interface, such as between
the MC68020 and a single MC68302, vector generation can be enabled. For this purpose,
the VGE bit is defined.
VGE—Vector Generation Enable
0 = In disable CPU mode, the MC68302 will not output interrupt vectors during inter-
rupt acknowledge cycles.
1 = In disable CPU mode, the MC68302 will output interrupt vectors for internal level 4
interrupts (and for levels 1, 6, and/or 7 as enabled in the interrupt controller) during
interrupt acknowledge cycles.
NOTE
Do not use the function code value “111” during external access-
es to the IMP, except during interrupt acknowledge cycles.
In disable CPU mode, the low-power modes will be entered immediately upon the setting of
the LPEN bit in the SCR by an external master. In this case, low-power mode will continue
until the LPEN bit is cleared. Users may wish to use a low-power mode in conjunction with
disable CPU mode to save power consumed by the disabled M68000 core.
All MC68302 functionality not expressly mentioned in this section is retained in disable CPU
mode and operates identically as before.
NOTE
Even without the use of the disable CPU logic, another proces-
sor can be granted access to the IMP on-chip peripherals by re-