Electrical Characteristics
MOTOROLA
MC68302 USER’S MANUAL
6-7
NOTES:
1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum
columns.
2. Actual value depends on clock period since signals are driven/latched on different CLKO edges. To calculate
the actual spec for other clock frequencies, the user may derive the formula for each specification. First, derive
the margin factor as: M = N(P/2) - Sa
where N is the number of one-half CLKO periods between the two events as derived from the timing diagram, P
is the rated clock period of the device for which the specs were derived (e.g., 60 ns with a 16.67-MHz device or
50 ns with a 20 MHz device), and Sa is the actual spec in the data sheet. Thus, for spec 14 at 16.67 MHz:
M = 5(60 ns/2) - 120 ns = 30 ns.
Once the margin (M) is calculated for a given spec, a new value of that spec (Sn) at another clock frequency
with period (Pa) is calculated as:
Sn = N(Pa/2) - M
Thus for spec 14 at 12.5 MHz:
Sn = 5(80 ns/2) - 30 ns = 170 ns.
These two formulas assume a 50% duty cycle. Otherwise, if N is odd, the previous values N(P/2) and N(Pa/2)
must be reduced by X, where X is the difference between the nominal pulse width and the minimum pulse width
of the EXTAL input clock for that duty cycle.
3.
If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is a
16.67 MHz
20 MHz
25 MHz
Num.
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
37
BGACK Asserted to BG Negated
t
GALGH
2.5
4.5
2.5
4.5
2.5
4.5
clks
37A
BGACK Asserted to BR Negated (see Note
8)
t
GALBRH
10
1.5
10
1.5
10
1.5
ns/
clks
38
BG Asserted to Control, Address, Data Bus
High Impedance (AS Negated)
t
GLZ
—
50
—
42
—
33
ns
39
BG Width Negated
t
GH
t
GALAV
t
GALASA
t
SHVPH
t
GAL
1.5
—
1.5
—
1.5
—
clks
40
BGACK Asserted to Address Valid
15
—
15
—
15
—
ns
41
BGACK Asserted to AS Asserted
30
—
30
—
20
—
ns
44
AS, DS Negated to AVEC Negated
0
50
0
42
0
33
ns
46
BGACK Width Low
1.5
—
1.5
—
1.5
—
clks
47
Asynchronous Input Setup Time (see Note
5)
BERR Asserted to DTACK Asserted (see
Notes 2 and 3)
t
ASI
10
—
10
—
7
—
ns
48
t
BELDAL
10
—
10
—
7
—
ns
53
Data-Out Hold from Clock High
t
CHDOI
0
—
0
—
0
—
ns
55
R/W Asserted to Data Bus Impedance
Change
t
RLDBD
0
—
0
—
0
—
ns
56
HALT/RESET Pulse Width (see Note 4)
t
HRPW
t
GASD
t
GAFD
10
—
10
—
10
—
clks
57
BGACK Negated to AS, DS, R/W Driven
1.5
—
1.5
—
1.5
—
clks
57A
BGACK Negated to FC
1
—
1
—
1
—
clks
58
BR Negated to AS, DS, R/W Driven (see
Note 7)
t
RHSD
1.5
—
1.5
—
1.5
—
clks
58A
BR Negated to FC (see Note 7)
t
RHFD
t
CHBCL
1
—
1
—
1
—
clks
60
Clock High to BCLR Asserted
—
30
—
25
—
20
ns
61
Clock High to BCLR High Impedance (See
Note 10)
Clock Low (S0 Falling Edge during read) to
RMC Asserted
t
CHBCH
—
30
—
25
—
20
ns
62
t
CLRML
—
30
—
25
—
20
ns
63
Clock High (during write) to RMC Negated
t
CHRMH
t
RMHGL
—
30
—
25
—
20
ns
64
RMC Negated to BG Asserted (see Note 9)
—
30
—
25
—
20
ns