MOTOROLA
MC68302 USER’S MANUAL
xvii
LIST OF FIGURES
Figure
Number
Title
Page
Number
Section 1
General Description
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
MC68302 Block Diagram ...........................................................................1-2
General-Purpose Microprocessor System Design.....................................1-4
MC68302 System Design...........................................................................1-5
NMSI Communications-Oriented Board Design.........................................1-7
Basic Rate IDL Voice/Data Terminal in ISDN ............................................1-8
Section 2
MC68000/MC68008 Core
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
M68000 Programming Model.....................................................................2-2
M68000 Status Register.............................................................................2-3
M68000 Bus/Address Error Exception Stack Frame................................2-10
M68000 Short-Form Exception Stack Frame...........................................2-10
MC68302 IMP Configuration Control .......................................................2-12
Section 3
System Integration Block (SIB)
IDMA Controller Block Diagram .................................................................3-3
Interrupt Controller Block Diagram...........................................................3-16
Interrupt Request Logic Diagram for SCCs..............................................3-21
SCC1 Vector Calculation Example...........................................................3-23
Parallel I/O Block Diagram for PA0..........................................................3-30
Parallel I/O Port Registers........................................................................3-33
RAM Block Diagram.................................................................................3-35
Timer Block Diagram................................................................................3-36
Chip-Select Block Diagram ......................................................................3-44
Figure 3-10. Using an External Crystal.........................................................................3-49
Figure 3-11. System Control Register ..........................................................................3-50
Figure 3-12. IMP Bus Arbiter........................................................................................3-57
Figure 3-13. DRAM Control Block Diagram..................................................................3-67
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Section 4
Communications Processor (CP)
Simplified CP Architecture..........................................................................4-2
Three Serial Data Flow Paths ....................................................................4-4
NMSI Physical Interface.............................................................................4-8
Multiplexed Mode on SCC1 Opens Additional Configuration
Possibilities.................................................................................................4-9
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.