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參數(shù)資料
| 型號(hào)： | MC68HC05BD3P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 41/112頁 |
| 文件大?。?/td> | 864K |
| 代理商： | MC68HC05BD3P |
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MOTOROLA
4-2
MC68HC05BD3
RESETS AND INTERRUPTS
4
4.1.3
Illegal Address (ILADR) Reset
The MCU monitors all opcode fetches. If an illegal address space is accessed during an opcode
fetch, an internal reset is generated. Illegal address spaces consist of all unused locations within
the memory map and the I/O registers (see Figure 3-1). Because the internal reset signal is used,
the MCU comes out of an ILADR reset in the same operating mode it was in when the opcode was
fetched.
4.1.4
Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specic amount of time by a program reset sequence.
Figure 4-1 Power-On Reset and RESET Timing
VDD
XTAL PIN1
INTERNAL
CLOCK2
INTERNAL
ADDRESS
BUS2
INTERNAL
DATA
BUS2
RESET
3FFE
3FFF
NEW PC
3FFE
3FFF
tVDDR
VDD THRESHOLD (TYPICALLY 1-2V)
4064 tcyc
toxov
tcyc
3
NEW
PCH
NEW
PCL
OP
CODE
tRL=1.5tCYC
PCH
PCL
OP
CODE
NEW PC
NOTES:
1. XTAL is not meant to represent frequency. It is only used to represent time.
2. Internal clock, internal address bus, and internal data bus signals are not available externally.
3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
TPG
32
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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