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參數(shù)資料
| 型號： | MC68HC05BD3P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 71/112頁 |
| 文件大小： | 864K |
| 代理商： | MC68HC05BD3P |
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MC68HC05BD3
MOTOROLA
8-1
SYNC SIGNAL PROCESSOR
8
SYNC SIGNAL PROCESSOR
The functions of the SSP include polarity correction, sync separation, sync pulse reshaper, sync
pulse detectors, horizontal line counter, vertical frequency counter, and free running signals
generator. In addition, interrupt can be generated for each vertical frame at a user specied
horizontal line number.
The processor accepts either composite or separate sync inputs.
For separate sync inputs, the HTTL and VTTL outputs are identical to the incoming horizontal sync
with negative sync polarity. As for composite sync input, reassembled horizontal sync pulses can
be inserted during the vertical sync period. The VTTL output is triggered by the leading edge of
the incoming vertical sync pulse, and the sync pulse will be widened by 9.5
s.
Both HSYNC and VSYNC inputs have internal lter to improve noise immunity. Any pulse that is
shorter than an internal bus clock period, will be regarded as a glitch, and will be ignored.
Note:
All quoted timings in this section are based on the assumption that the internal bus
frequency is 2MHz, i.e. tCYC=0.5s.
8.1
Functional Blocks
The architecture of the Sync Signal Processor is shown in Figure 8-1. Each of the functional
blocks are described in the following paragraphs.
8.1.1
Polarity Correction
The polarity correction block of the sync signal processor accepts the input sync signals
(HSYNC/VSYNC) and converts them to negative polarity signals, regardless of the polarity of the
inputs. The following describes the methodologies used in polarity correction.
TPG
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Freescale Semiconductor, Inc.
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