參數(shù)資料
型號： MC68HC05BD3P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 59/112頁
文件大小： 864K
代理商： MC68HC05BD3P
MOTOROLA
7-4
MC68HC05BD3
M-BUS SERIAL INTERFACE
7
7.2.3
Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a
direction specied by the R/W bit sent by the calling master.
Each data byte is 8 bits long. Data can be changed only when SCL is low and must be held stable
when SCL is high as shown in Figure 7-2. One clock pulse is for one bit of data transfer, MSB is
transferred rst. Each data byte has to be followed by an acknowledge bit. Hence, one complete
data byte transfer requires 9 clock pulses.
If the slave receiver does not acknowledge the master, the SDA line should be left high by the
slave, the master can then generate a STOP signal to abort the data transfer or a START signal
(repeated START) to commence a new calling.
If the master receiver does not acknowledge the slave transmitter after one byte transmission, it
means an “end of data” to the slave. The slave shall release the SDA line for the master to
generate STOP or START signal.
7.2.4
Repeated START Signal
As shown in Figure 7-2, a repeated START signal is to generate a START signal without rst
generating a STOP signal to terminate the communication. This is used by the master to
communicate with another slave or with the same slave in a different mode (transmit/receive
mode) without releasing the bus.
7.2.5
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus.
However, the master may generate a START signal followed by a calling command without
generating a STOP signal rst. This is called repeat START. A STOP signal is dened as a low to
high transition of SDA while SCL is at a logical high; see Figure 7-2.
7.2.6
Arbitration Procedure
This interface circuit is a true multi-master system which allows more than one master to be
connected. If two or more masters try to control the bus at the same time, a clock synchronization
procedure determines the bus clock. The clock low period is equal to the longest clock low period
among the masters; and the clock high period is the shortest among the masters. A data
arbitration procedure determines the priority. A master will lose arbitration if it transmits a logic “1”
while the others transmit logic “0”, the losing master will immediately switch over to slave receive
mode and stops its data and clock outputs. The transition from master to slave mode will not
generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of
arbitration.
TPG
48
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
MC68HC05C9AFNR2 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC05C9AFNR2 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC05C9ACFNR2 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQCC44
MC68HC05C9AMB 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
MC68HC05C9AMFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC05BD5 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
MC68HC05C0CP 制造商:Motorola Inc 功能描述:
MC68HC05C12 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C12B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C12CP 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*