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| 型號： | MC68HC05BD3P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 82/112頁 |
| 文件大小： | 864K |
| 代理商： | MC68HC05BD3P |
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MC68HC05BD3
MOTOROLA
8-11
SYNC SIGNAL PROCESSOR
8
8.4
System Operation
The incoming signals can be either separate HSYNC and VSYNC or composite sync through
HSYNC input. Polarity correction is performed before the sync signals go any further into the
system. The sync pulse detection block continuously monitors the signals to see if the signals are
active. If the signals are not active, the circuit switches to output the internally generated sync
signals. This will protect the circuits behind from being damaged by inactive signals.
A typical monitor system operation is summarized in Figure 8-6.
Note:
User is required to check the HDET and VDET at VSIN=0 rst. If either or both are not
detected, user then set VSIN=1 to check HDET and VDET. It is because if the incoming
signal is a valid composite signal, HDET and VDET are both read 1 even VSIN=1.
Note:
Each time if VDET is not detected when VSIN=1, user needs to clear VSIN to check
VDET. If VDET is still not detected, user then set VSIN to check them again to decide
what mode it is.
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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